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參數(shù)資料
| 型號： | KM29W32000T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 8 Bit NAND Flash Memory(4M x 8 位 NAND閃速存儲器) |
| 中文描述： | 4米× 8位NAND閃存（4米× 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 316K |
| 代理商： | KM29W32000T |
KM29W32000T, KM29W32000IT
FLASH MEMORY
3
512B Column
16B Column
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Figure 2. ARRAY ORGANIZATION
NOTE
: Column Address : Starting Address of the Register.
00H Command(Read) : Defines the starting Address of the 1st half of the Register.
01H Command(Read) : Defines the sarting Address of the 2nd half of the Register.
* A
8
is initially set to "Low" or "High" by the 00H or 01H Command.
* X can be High or Low.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2nd Cycle
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
3rd Cycle
A
17
A
18
A
19
A
20
A
21
*X
*X
*X
V
CC
V
SS
X-Buffers
Latches
& Decoders
Y-Gating
32M + 1M Bit
NAND Flash
ARRAY
Command
Register
2nd half Page Register & S/A
(512 + 16)Byte x 8192
Y-Gating
1st half Page Register & S/A
I/O Buffers & Latches
Y-Buffers
Latches
& Decoders
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
A
9
- A
21
A
0
- A
7
Command
RE
WE
CLE ALE WP
I/0 0
I/0 7
V
CC
Q
V
SS
A
8
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
32M : 8K Row
(=512 Block)
512Byte
8 bit
16Byte
1 Block(=16 Row)
(8K + 256) Byte
I/O 0 ~ I/O 7
1 Page = 528 Bytes
1 Block = 528 B x 16 Pages
= (8K + 256) Bytes
1 Device = 528B x 16Pages x 512 Blocks
= 33 Mbits
Column Address
Row Address
(Page Address)
Page Register
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