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參數(shù)資料
| 型號： | KM29W32000T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 8 Bit NAND Flash Memory(4M x 8 位 NAND閃速存儲器) |
| 中文描述： | 4米× 8位NAND閃存（4米× 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 316K |
| 代理商： | KM29W32000T |
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KM29W32000T, KM29W32000IT
FLASH MEMORY
2
4M x 8 Bit NAND Flash Memory
The KM29W32000 is a 4M(4,194,304)x8bit NAND Flash Mem-
ory with a spare 128K(131,072)x8bit. Its NAND cell provides
the most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typically 250
μ
s and an erase operation can be performed in
typically 2ms on an 8K-byte block.
Data in the page can be read out at 50ns cycle time per byte.
The I/O pins serve as the ports for address and data input/out-
put as well as command inputs. The on-chip write controller
automates all program and erase system functions, including
pulse repetition, where required, and internal verify and margin-
ing of data. Even the write-intensive systems can take advan-
tage of the KM29W32000 extended reliability of one million
program/erase cycles by providing either ECC(Error Correction
Code) or real time mapping-out algorithm. These algorithms
have been implemented in many mass storage applications
and also the spare 16 bytes of a page combined with the other
512 bytes can be utilized by system-level ECC.
The KM29W32000 is an optimum solution for large nonvolatile
storage application such as solid state storage, digital voice
recorder, digital still camera and other portable applications
requiring nonvolatility.
GENERAL DESCRIPTION
FEATURES
Voltage Supply : 2.7V ~ 5.5V
Organization
- Memory Cell Array : (4M + 128K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
- Status Register
528-Byte Page Read Operation
- Random Access : 10
μ
s(Max.)
- Serial Page Access : 50ns(Min.)
Fast Write Cycle Time
- Program time : 250
μ
s(typ.)
- Block Erase time : 2ms(typ.)
Command/Address/Data Multiplexed I/O port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 1M Program/Erase Cycles
- Data Retention : 10 years
Command Register Operation
44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
- Forward Type
PIN CONFIGURATION
NOTE
: Connect all V
CC,
V
CC
Q and V
SS
pins of each device to power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
V
SS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
Q
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
SE
R/B
RE
CE
V
CC
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44(40) TSOP (II)
STANDARD TYPE
Pin Name
Pin Function
I/O0 ~ I/O7
Data Inputs/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
SE
Spare area Enable
R/B
Ready/Busy output
V
CC
Power(2.7V ~ 5.5V)
V
CC
Q
Output Butter Power(2.7V ~ 5.5V)
V
Ground
N.C
No Connection
PIN DESCRIPTION
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