參數(shù)資料
型號(hào)： KM29W32000T
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4M x 8 Bit NAND Flash Memory(4M x 8 位 NAND閃速存儲(chǔ)器)
中文描述： 4米× 8位NAND閃存（4米× 8位的NAND閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 24/26頁(yè)
文件大小： 316K
代理商： KM29W32000T
KM29W32000T, KM29W32000IT
FLASH MEMORY
24
Figure 10. RESET Operation
RESET
The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during rand om
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data regist ers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0H when WP is
high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/ B pin transitions to low for t
RST
after the Reset command is written. Reset command is
not necessary for normal operation. Refer to Figure 10 below.
Table3. Device Status
After Power-up
After Reset
Operation Mode
Read 1
Waiting for next command
FFH
I/O
0
~
7
R/B
t
RST
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage dete ctor
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V
IL
during power-up and power-down as shown in Figure 8. The two step command sequence for program/erase provides additional
software protection.
Figure 8. AC Waveforms for Power Transition
V
CC
WP
High
≈
≈
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