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| 型號： | KAD5510P-50Q72 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 500MSPS SGL 72-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 438mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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17
FN6811.2
October 8, 2009
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
is illustrated in Figure 30.
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The nominal value of the voltage
reference is 1.25V.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. In either case, the data
is presented in double data rate (DDR) format. Figures 1
and 2 show the timing relationships for LVDS and CMOS
modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user
should experiment to determine if performance degradation
is observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in “Serial Peripheral Interface” on
An external resistor creates the bias for the LVDS drivers. A
10k
Ω, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over-Range Indicator
The over-range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary
mode). The output code does not wrap around during an
over-range condition. The OR bit is updated at the sample
rate.
Power Dissipation
The power dissipated by the KAD5510P-50 is primarily
dependent on the sample rate and the output modes: LVDS
vs CMOS and DDR vs SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation changes to a lesser degree in LVDS mode, but is
more strongly related to the clock frequency in CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power
saving modes are available: Nap, and Sleep. Nap mode
reduces power dissipation to less than 163mW and recovers
to normal operation in approximately 1s. Sleep mode
reduces power dissipation to less than 6mW but requires
approximately 1ms to recover from a sleep command.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during
sleep, requiring a user to wait 150s max after CSB is
asserted (brought low) prior to writing ‘001x’ to SPI
Register 25. The device would be fully powered up, in
normal mode 1ms after this command is written.
Wake-up from Sleep Mode Sequence (CSB high)
Pull CSB Low
Wait 150s
Write ‘001x’ to Register 25
Wait 1ms until ADC fully powered on
SNR
20 log
10
1
2
πf
IN tJ
--------------------
=
(EQ. 1)
FIGURE 30. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
SN
R
(
d
B
)
INPUT FREQUENCY (Hz)
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
KAD5510P-50
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相關(guān)代理商/技術(shù)參數(shù) |
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| KAD5512HP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
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| KAD5512HP-12Q48 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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