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參數(shù)資料
| 型號： | KAD5510P-50Q72 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 500MSPS SGL 72-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 438mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
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20
FN6811.2
October 8, 2009
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK)
serial data input (SDI), and serial data input/output (SDIO).
The maximum SCLK rate is equal to the ADC sample rate
(fSAMPLE) divided by 32 for write operations and fSAMPLE
divided by 132 for reads. At fSAMPLE = 250MHz, maximum
SCLK is 15.63MHz for writing and 3.79MHz for read
operations. There is no minimum SCLK rate.
The following sections describe various registers that are
used to configure the SPI or adjust performance or functional
parameters. Many registers in the available address space
(0x00 to 0xFF) are not defined in this document. Additionally,
within a defined register there may be certain bits or bit
combinations that are reserved. Undefined registers and
undefined values within defined registers are reserved and
should not be selected. Setting any reserved register or value
may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the
data transfer. By default, all data is presented on the serial
data input/output (SDIO) pin in three-wire mode. The state of
the SDIO pin is set automatically in the communication
protocol (described in the following paragraphs). A dedicated
serial data output pin (SDO) can be activated by setting
0x00[7] high to allow operation in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5510P-50 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an
unaddressed device is asserted in four wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
read from at a given time (again, only in three-wire mode). If
multiple slave devices are selected for reading at the same
time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition Data can
be presented in MSB-first order or LSB-first order. The
default is MSB-first, but this can be changed by setting
ordering for the MSB-first and LSB-first modes, respectively.
In MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits,
W1 and W0, determine the number of data bytes to be read
or written (see Table 6). The lower 13 bits contain the first
address for the data transfer. This relationship is illustrated in
Figure 35, and timing values are given in “Switching
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from
the ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active.
Stalling of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or
more, CSB is allowed stall in the middle of the
instruction/address bytes or before the first data byte. If CSB
FIGURE 37. 2-BYTE TRANSFER
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
CSB STALLING
FIGURE 38. N-BYTE TRANSFER
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
LAST LEGAL
CSB STALLING
KAD5510P-50
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PDF描述 |
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| KAD5512HP-17Q72 | IC ADC 12BIT 170MSPS SGL 72-QFN |
| KAD5512P-17Q72 | IC ADC 12BIT 170MSPS SGL 72-QFN |
| KAD5514P-12Q72 | IC ADC 14BIT 125MSPS SGL 72-QFN |
| KAD5610P-25Q72 | IC ADC 10BIT 250MSPS DUAL 72-QFN |
| KAD5612P-17Q72 | IC ADC 12BIT 170MSPS DUAL 72-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KAD5512HP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP_09 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP_0910 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP-12Q48 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| KAD5512HP-12Q72 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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