參數(shù)資料
型號： KAD5510P-50Q72
廠商： Intersil
文件頁數(shù)： 7/29頁
文件大?。?/td> 0K
描述： IC ADC 10BIT 500MSPS SGL 72-QFN
產品培訓模塊： High-Speed Analog-to-Digital Converters
標準包裝： 1
系列： FemtoCharge™
位數(shù)： 10
采樣率（每秒）： 500M
數(shù)據(jù)接口： 串行，SPI?
轉換器數(shù)目： 1
功率耗散（最大）： 438mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應商設備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，單極
15
FN6811.2
October 8, 2009
The SDO pin requires an external 4.7k
Ω pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should be
connected to an open-drain driver with a drive strength of
less than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 22. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output returns
to normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range
condition the OR pin will stay high, and it will not be possible
to detect the end of the calibration cycle.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 500MSPS
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
User Initiated Reset
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength of less than
0.5mA is recommended, RESETN has an internal high
impedance pull-up to OVDD. As is the case during power-on
reset, the SDO, RESETN and DNC pins must be in the
proper state for the calibration to successfully execute.
The performance of the KAD5510P-50 changes with
variations in temperature, supply voltage or sample rate. The
extent of these changes may necessitate recalibration,
depending on system performance requirements. Best
performance will be achieved by recalibrating the ADC under
the environmental conditions at which it will operate.
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.1dBFS and SFDR
change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less than
80MSPS will typically result in an SNR change of less than
0.1dBFS and an SFDR change of less than 3dBc.
Figures 23 and 24 show the effect of temperature on SNR
and SFDR performance with calibration performed at -40°C,
+25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single calibration at
-40°C, +25°C and +85°C. Best performance is typically
achieved by calibration at the operating conditions as stated
earlier but it can be seen that performance drift with
temperature is not a very strong function of the temperature
at which the calibration is performed.
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 1.45V, centered at the VCM voltage
of 0.535V as shown in Figure 25.
FIGURE 22. CALIBRATION TIMING
CLKP
CLKN
CLKOUTP
RESETN
ORP
CALIBRATION
BEGINS
CALIBRATION
COMPLETE
CALIBRATION
TIME
FIGURE 23. SNR PERFORMANCE vs TEMPERATURE
-4
-3
-2
-1
0
1
2
3
-40
-15
10
35
60
85
SNR
CHANGE
(
d
Bf
s)
CAL DONE AT
+85°C
TEMPERATURE (°C)
CAL DONE AT
-40°C
CAL DONE AT
+25°C
FIGURE 24. SFDR PERFORMANCE vs TEMPERATURE
-15
-10
-5
0
5
10
15
-40
-15
10
35
60
85
SFDR
C
HANGE
(d
Bc
)
TEMPERATURE (°C)
CAL DONE AT
-40°C
CAL DONE AT
+25°C
CAL DONE AT
+85°C
KAD5510P-50
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