參數(shù)資料
型號: KAD5510P-50Q72
廠商: Intersil
文件頁數(shù): 28/29頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 500MSPS SGL 72-QFN
產(chǎn)品培訓(xùn)模塊: High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝: 1
系列: FemtoCharge™
位數(shù): 10
采樣率(每秒): 500M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 438mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,單極
8
FN6811.2
October 8, 2009
Pinout/Package Information
Pin Descriptions
PIN NUMBER
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
1, 6, 12, 19, 24, 71
AVDD
1.8V Analog Supply
2-5, 13, 14, 17, 18, 28-35
DNC
Do Not Connect
7, 8, 11, 72
AVSS
Analog Ground
9, 10
VINN, VINP
Analog Input Negative, Positive
15
VCM
Common Mode Output
16
CLKDIV
Clock Divider Control
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
Output Mode (LVDS, LVCMOS)
23
NAPSLP
Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low, See “User Initiated Reset” on page 15)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
37
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
38
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[ LVCMOS Bit 0]
39
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
40
D1P
[D1]
LVDS Bit 1 Output True
[ LVCMOS Bit 1]
41
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
42
D2P
[D2]
LVDS Bit 2 Output True
[ LVCMOS Bit 2]
43
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
44
D3P
[D3]
LVDS Bit 3 Output True
[ LVCMOS Bit 3]
46
RLVDS
LVDS Bias Resistor (connect to OVSS with a 10k
Ω, 1% resistor)
47
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
49
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
50
D4P
[D4]
LVDS Bit 4 Output True
[ LVCMOS Bit 4]
51
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
52
D5P
[D5]
LVDS Bit 5 Output True
[ LVCMOS Bit 5]
53
D6N
[NC]
LVDS Bit 6 Output Complement
[NC in LVCMOS]
54
D6P
[D6]
LVDS Bit 6 Output True
[ LVCMOS Bit 6]
KAD5510P-50
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