參數資料
型號： K4J55323QF-GC20
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit GDDR3 SDRAM
中文描述： 片256Mbit GDDR3 SDRAM的
文件頁數： 47/49頁
文件大?。?/td> 1027K
代理商： K4J55323QF-GC20
- 47 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
AC CHARACTERISTICS - I
Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks(this case can be used regardless of fre
quency), the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to
4 ~7 clocks , the input buffers are turned on during the WRITE commands for lower power operation. The WRITE latency which is over 4 clocks
can be used only in case that Write Latency*tCK is greater than 7ns.
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by
the on-die termination alone.
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
Parameter
Symbol
-14
-15
-16
-20
Unit
Note
Min
-0.26
Max
+0.26
Min
-0.26
Max
+0.26
Min
-0.29
Max
+0.29
Min
-0.35
Max
+0.35
DQS out access time from CK
t
DQSCK
t
CH
t
CL
ns
CK high-level width
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
0.45
1.4
-
-
5
0.55
3.3
-
-
-
0.45
1.4
-
-
5
0.55
3.3
-
-
-
0.45
-
1.6
-
5
0.55
-
3.3
-
-
0.45
-
-
2.0
4
0.55
-
-
3.3
-
tCK
ns
ns
ns
tCK
CK cycle time
CL=9
CL=8
CL=7
t
CK
WRITE Latency
t
WL
t
DH
t
DS
t
ATS
t
ATH
t
DQSH
t
DQSL
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRE
t
WPRES
t
WPST
1
DQ and DM input hold time relative to DQS
0.18
-
0.18
-
0.20
-
0.25
-
ns
DQ and DM input setup time relative to DQS
0.18
-
0.18
-
0.20
-
0.25
-
ns
Active termination setup time
10
-
10
-
10
-
10
ns
Active termination hold time
10
-
10
-
10
-
10
-
ns
DQS input high pulse width
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
DQS input low pulse widthl
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Data strobe edge to Dout edge
-
0.160
-
0.160
-
0.180
-
0.225
ns
DQS read preamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS read postamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2
tCK
DQS write preamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
2
DQS write preamble setup time
0
-
0
-
0
-
0
-
ns
DQS write postamble
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
3
Half strobe period
t
HP
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
t
HP
-
0.225
-0.3
-
tCK
Data output hold time from DQS
t
QH
t
HP
-0.16
-
t
HP
-0.16
-
t
HP
-0.18
-
-
ns
Data-out high-impedance window from CK and /CK t
HZ
Data-out low-impedance window from CK and /CK t
LZ
Address and control input hold time
-0.3
-
-0.3
-
-0.3
-
-
ns
4
-0.3
-
-0.3
-
-0.3
-
-0.3
-
ns
4
t
IH
t
IS
t
IPW
0.35
-
0.35
-
0.4
-
0.5
-
ns
Address and control input setup time
0.35
-
0.35
-
0.4
-
0.5
-
ns
Address and control input pulse width
1.0
-
1.0
-
1.1
-
1.3
-
ns
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