參數(shù)資料
型號(hào): K4J55323QF-GC20
廠(chǎng)商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256Mbit GDDR3 SDRAM
中文描述: 片256Mbit GDDR3 SDRAM的
文件頁(yè)數(shù): 15/49頁(yè)
文件大小: 1027K
代理商: K4J55323QF-GC20
- 15 -
256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
The extended mode register stores the data output driver strength and on-die termination options. The
extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis-
ter). The state of address pins A0 ~ A11 and BA0 in the same cycle as CS, RAS, CAS and WE going low are
written in the extended mode register. Six clock cycles are required to complete the write operation in the
extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The
mode register contents can be changed using the same command and clock cycle requirements during opera-
tion as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
EXTENDED MODE REGISTER SET(EMRS)
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DLL
A
6
0
1
DLL
Enable
Disable
Additive Latency
A
9
0
0
1
1
A
8
0
1
0
1
AL
0
1
Reserved
Reserved
0
1
LP
ID
AL
tWR
DLL
tWR
Termination
Drive Strength
BA
0
0
1
A
n
~ A
0
MRS
EMRS
Low Power
A
11
0
1
Low Power
Disable
Enable
Vendor ID
A
10
0
1
Vendor ID
Off
On
tWR
A
7
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
tWR
3
4
5
6
7
Reserved
Reserved
Reserved
Drive Strength
A
1
0
0
1
1
A
0
0
1
0
1
Drive Strength
Autocal
30
40
50
Termination
A
3
0
0
1
1
A
2
0
1
0
1
Termination
ODT Disabled
Reserved
ZQ/4
ZQ/2
* ZQ : Resistor connection pin for On-die termination
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