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參數(shù)資料
| 型號： | K4J55323QF-GC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit GDDR3 SDRAM |
| 中文描述： | 片256Mbit GDDR3 SDRAM的 |
| 文件頁數(shù)： | 22/49頁 |
| 文件大小： | 1027K |
| 代理商： | K4J55323QF-GC20 |
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256M GDDR3 SDRAM
K4J55323QF-GC
Rev 1.8 (Apr. 2005)
OPERATIONS
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM,
a row in that bank must be "opened." This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued
to that row, subject to the t
RCD
specification. t
RCD(min)
should be divided by the clock period
and rounded up to the next whole number to determine the earliest clock edge after the
ACTIVE command in which a READ or WRITE command can be entered. For example, a t
RCD
specification of 16ns with a 450MHz clock (2.2ns period) results in 7.2 clocks rounded to 8.
This is reflected in below figure, which covers any case where 7<t
RCD(min)
/t
CK
≤
8.
The same procedure is used to convert other specification limits from tome units to clock
cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued after
the previous active row has been "closed"(precharged). The minimum time interval between
successive ACTIVE commads to the same bank is defined by t
RC
.
A subsequent ACTIVE command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row access overhead. The minimum time inter-
val between successive ACTIVE commands to different banks is defined by t
RRD
.
/CK
CK
RA
CKE
/CS
/RAS
/CAS
/WE
A0-A11
BA0,1
HIGH
BA
RA = Row Address
BA = Bank Address
Activating a Specific Row
in a Specific Bank
T0
T1
T3
T4
T7
/CK
CK
COMMAND
T8
A0-A11
T2
T9
～
～
ACT
NOP
NOP
ACT
NOP
NOP
RD/WR
NOP
Row
Row
Col
BA0, BA1
Bank x
Bank y
Bank y
t
RRD
t
RCD
～
～
～
～
～
～
DON’T CARE
Example : Meeting t
RCD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4M51163LE | 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M51163LE-F | 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M51163LE-L | 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M51163LE-YC | 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M51163LE-YF1L | 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4J55323QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG-BC12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG-BC14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG-BC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
| K4J55323QG-BC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM |
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