參數(shù)資料
型號: K1S2816BCM-I
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: TPS54262EVM Evaluation Module
中文描述: 8M × 16位位的頁面模式統(tǒng)一晶體管隨機(jī)存取存儲器
文件頁數(shù): 9/10頁
文件大?。?/td> 146K
代理商: K1S2816BCM-I
Revision 1.0
April 2005
K1S2816BCM
- 9 -
U
t
RAM
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS
1
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
1
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS
1
going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
is applied in case a write ends with CS
1
or WE going high.
5. t
WP
(min)=70ns for continuous write operation over 50 times.
t
WC
t
CW
t
BW
t
WP
t
DH
t
DW
t
WR
t
AW
t
AS
CS
1
CS
2
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
t
WC
t
CW
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR
t
AS
CS
1
CS
2
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