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參數資料
| 型號： | JZ48F4L0QTZ |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數： | 60/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | JZ48F4L0QTZ |
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Intel StrataFlash Wireless Memory (L18)
April 2005
60
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
When Buffered Programming has completed, additional buffer writes can be initiated by issuing
another Buffered Programming Setup command and repeating the buffered program sequence.
Buffered programming may be performed with V
PP
= V
PPL
or V
PPH
(see
Section 5.2, “Operating
Conditions” on page 25
for limitations when operating the device with V
PP
= V
PPH
).
If an attempt is made to program past an erase-block boundary using the Buffered Program
command, the device aborts the operation. This generates a command sequence error, and Status
Register bits SR[5,4] are set.
If Buffered programming is attempted while V
PP
is below V
PPLK
, Status Register bits SR[4,3] are
set. If any errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
11.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash
programming for today's beat-rate-sensitive manufacturing environments. The enhanced
programming algorithm used in Buffered EFP eliminates traditional programming elements that
drive up overhead in device programmer systems.
Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see
Figure 42, “Buffered
EFP Flowchart” on page 88
). It uses a write buffer to spread MLC program performance across 32
data words. Verification occurs in the same phase as programming to accurately program the flash
memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This enhancement
eliminates three write cycles per buffer: two commands and the word count for each set of 32 data
words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0]
indicates when data from the buffer has been programmed into sequential flash memory array
locations.
Following the buffer-to-flash array programming sequence, the Write State Machine (WSM)
increments internal addressing to automatically select the next 32-word array boundary. This
aspect of Buffered EFP saves host programming equipment the address-bus setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s internal
verification to ensure that the device has programmed properly. This eliminates the external post-
program verification and its associated overhead.
11.3.1
Buffered EFP Requirements and Considerations
Buffered EFP requirements:
Ambient temperature: T
A
= 25
°C,
±5
°C
V
CC
within specified operating range.
VPP driven to V
PPH
.
Target block unlocked before issuing the Buffered EFP Setup and Confirm commands.
The first-word address (WA0) for the block to be programmed must be held constant from the
setup phase through all data streaming into the target block, until transition to the exit phase is
desired.
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