參數(shù)資料
型號(hào)： JZ48F4L0QTZ
廠商： Intel Corp.
英文描述： StrataFlash Wireless Memory
中文描述： 無(wú)線的StrataFlash存儲(chǔ)器
文件頁(yè)數(shù)： 50/106頁(yè)
文件大?。?/td> 1272K
代理商： JZ48F4L0QTZ
Intel StrataFlash Wireless Memory (L18)
April 2005
50
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
10.0
Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see
Section 10.3, “Read Configuration Register (RCR)” on page 51
).
Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read
Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read
Array. To change a partition’s read state, the appropriate read command must be written to the
device (see
Section 9.2, “Device Commands” on page 47
). See
Section 15.0, “Special Read States”
on page 75
for details regarding Read Status, Read ID, and CFI Query modes.
The following sections describe read-mode operations in detail.
10.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and all
partitions are set to Read Array. However, to perform array reads after any other device operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note:
Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see
Section 10.3, “Read Configuration Register (RCR)” on page 51
).
To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and
ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during
asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low
throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If
only asynchronous reads are to be performed, CLK should be tied to a valid V
IH
level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after
an initial access time t
AVQV
delay. (see
Section 7.0, “AC Characteristics” on page 28
).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:0] is driven onto DQ[15:0] after the initial access delay. Address bits A[MAX:2] select
the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the
data buffer at any given time.
10.2
Synchronous Burst-Mode Read
Section 10.3, “Read Configuration Register (RCR)” on page 51
continuous-wordsTo perform a
synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and ADV# are
asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then
deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access,
in which case the address is latched on the next valid CLK edge while ADV# is asserted.
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