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參數(shù)資料
| 型號(hào)： | ISPPAC30-01SI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大小： | 379K |
| 代理商： | ISPPAC30-01SI |
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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
21
Table 4. JTAG Configuration Register (CFG) Bits
Table 5. JTAG UES Register and ESF Bits
Auto-Calibration Mode
Every time the ispPAC30 is powered up, an automatic auto-calibration sequence is initiated. If this adversely affects
system operation, provisions must be incorporated that minimize the result as auto-calibration cannot be defeated.
The auto-calibration of the ispPAC30 effectively isolates it from external connections and drives the inputs of the
device to 0V and checks to see that there is zero offset at the outputs. This check is done maintaining the input-to-
Symbol
Name
Description
ARP Bits
Analog Routing Pool Bits
These various bits control the interconnect from input pins to IA’s and
MDACs, as well as where the VREF’s go and which input resources are
summed with one OA or the other and whether those OA’s are fed back to
any of the input cells.
Any of the six input devices, IA1, IA2, IA3, IA4, MDAC1 and MDAC2 can be
selected independently to have auto calibration performed with 0V (default)
or 2.5V applied to their inputs. Because of common-mode errors, choose
the level closest to the operating levels for the lowest offset after an auto-cal
operation.
This bit can set the device for dedicated SPI mode operation without any
external strapping of the pin being required. Note that normal JTAG opera-
tions cannot occur, such as programming by PAC-Designer when SPI mode
is enabled.
Bits to control the seven capacitors of each of OA’s.
These bits determine the gain of IA1, IA2, IA3, and IA4 (from 1 to 10).
These bits determine polarity of IA1, IA2, IA3, and IA4 (positive or inverted).
Bits to control the code settings of MDAC1 and MDAC2.
Determines via programmed bits whether a logic high activates input a or b
of either of the multiplexers in front of IA1 and IA4.
Programs whether MSEL1 and MSEL2 have internal pull-ups or pull-downs.
Determines through various bits whether OA1 and OA2 are acting as
fi
lters
(both feedback resistor and capacitor in circuit), or as integrators (only the
capacitor in feedback), or as comparators (neither feedback resistor or
capacitor in circuit).
Either or both of the output ampli
fi
ers can be commanded in power-down
mode without the rest of the chip having to be powered down. In this state,
their outputs are effectively in high-impedance mode.
A number of pins on the PAC30 have internal, programmable pull-up and
pull-down capability. See the pin description table in the speci
fi
cation sec-
tion for details on which pins and their default (shipped) states.
The serial digital data output pin has two output slew rates. The default is
low to reduce digital disruption of the analog circuitry. Sometimes a higher
slew rate is needed, so it is provided as a programmable option.
These bits set any of the seven available voltage outputs of VREF1 and
VREF2.
CALSEL
CAL Level Select
Enable SPI Mode Pull-up
FBCAP
IAGAIN
IAPOL
MDACCode
Feedback Capacitor
Input Ampli
fi
er Gain
Input Ampli
fi
er Polarity
MDAC Code
MSELPOL
MUX Select 1 & 2 Polarity
MSELPU1/2
MUX Select 1 & 2 PU/PD
OACFG
Output Amp Con
fi
guration
OAPD1/2
Output Amp Power-Down
PU/PD Bits
Pull-Up/Down
TDOSlew Bit
TDO Slew Rate
VREF1, VREF2
Voltage References 1 and 2
Symbol
Name
Description
UES Bits
User Electronic Signature
These are uncommitted E
2
bits that can be used to store device information
for future reference. The ispPAC30 contains 16 UES bits. These bits are
accessible from within PAC-Designer by using the Edit Symbol, UES Bits
command.
Setting this bit causes all subsequent readouts of the device con
fi
guration
to be disabled (JTAG Verify commands). Can be reset by performing a
JTAG user bulk erase command and reprogramming the device. This fea-
ture is used to prevent unauthorized readout of the device’s con
fi
guration.
ESF
Electronic Security Fuse
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| ISPPAC80-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01SI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC81-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81-01SI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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