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參數(shù)資料
| 型號(hào)： | ISPPAC30-01SI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 379K |
| 代理商： | ISPPAC30-01SI |
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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
20
Table 3. Precision Filter Configuration Ranges
Power-Down Mode
The ispPAC30 features a power-down mode whereby the current consumption of the device is reduced to a few
microamps. In this mode, the logic sections of the device are still fully active, but draw very little power. This means
communication can be maintained with the device while it is in the powered-down state. In the analog sections, the
bias currents are reduced or turned off and all sections that can be, are shut down. The analog outputs go to a high
impedance state in power-down mode. The maximum current in shutdown mode and the time required to resume
normal operation all are speci
fi
ed in the speci
fi
cations section of this data sheet. Programming or erasing of the E
2
con
fi
guration memory is not supported when an ispPAC30 is powered down. Power-down mode is commanded by
lowering the
PD
pin to a logic low, or by commanding it through JTAG or SPI serial mode commands.
In addition to full power-down mode, either of the output ampli
fi
ers can be shut down independently of all other cir-
cuitry. This can be done at any time by setting internal E
2
bits under JTAG or SPI command to reduce power con-
sumption while the rest of the ispPAC30 is in normal operation. This could also be accomplished at the time the
device is programmed initially via dialog box commands available in the PAC-Designer software. Note: Any IA or
MDAC that has nothing connected to its input is also automatically shut down.
JTAG User Con
fi
gurable Bits
There are a number of user-con
fi
gured E
2
bits that control all aspects of ispPAC30. These bits can all be accessed
somewhere in either the pull-down menus or directly in the schematic design entry screen of the PAC-Designer soft-
ware used to interface to the ispPAC30. See the online help associated with the ispPAC30 in PAC-Designer for more
details of how to set/program various operation modes. The list of control E
2
bits available are listed in Tables 4 and 5.
Feedback
Capacitor #
1
2
3
4
5
6
7
OA1 Feedback
Capacitor Value (pF)
4.320pF
7.156pF
11.97pF
18.16pF
27.29pF
42.37pF
64.01pF
Minimum Corner
Frequency (kHz)
63
41
25
17
11
7
5
Maximum Corner
Frequency (kHz)
619
401
250
169
114
74
49
Frequency Step
(kHz)
4.86
3.13
1.95
1.31
0.88
0.58
0.38
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| ISPPAC80-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01SI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC81-01PI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81-01SI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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