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| 型號(hào)： | ISPMACH4ACPLDFAMILY |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | 高的E 2的CMOS在系統(tǒng)可編程邏輯 |
| 文件頁數(shù)： | 20/62頁 |
| 文件大小： | 1180K |
| 代理商： | ISPMACH4ACPLDFAMILY |
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20
ispMACH 4A Family
ispMACH 4A TIMING MODEL
The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a
ispMACH 4A device, and at the same time, be easy to understand. This model accurately
describes all combinatorial and registered paths through the device, making a distinction
between internal feedback and external feedback. A signal uses internal feedback when it is fed
back into the switch matrix or block without having to go through the output buffer. The input
register specifications are also reported as internal feedback. When a signal is fed back into the
switch matrix after having gone through the output buffer, it is using external feedback.
The parameter, t
BUF
, is defined as the time it takes to go from feedback through the output buffer
to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter
designator is followed by an “i”. By adding t
BUF
to this internal parameter, the external parameter
is derived. For example, t
PD
= t
PDi
+ t
BUF
. A diagram representing the modularized ispMACH 4A
timing model is shown in Figure 15. Refer to the application note entitled
MACH 4 Timing and
High Speed Design
for a more detailed discussion about the timing parameters.
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual
macrocell with the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is
independent of the logic required by the design. Other competitive CPLDs incur serious timing
delays as product terms expand beyond their typical 4 or 5 product term limits. Speed
and
SpeedLocking combine to give designs easy access to the performance required in today’s
designs.
(External Feedback)
(Internal Feedback)
INPUT REG/
INPUT LATCH
t
SIRS
t
HIRS
t
SIL
t
HIL
t
SIRZ
t
HIRZ
t
SILZ
t
HILZ
t
PDILi
t
ICOSi
t
IGOSi
t
PDILZi
Q
t
SS(T)
t
SA(T)
t
H(S/A)
t
S(S/A)L
t
H(S/A)L
t
SRR
t
PDi
t
PDLi
t
CO(S/A)i
t
GO(S/A)i
t
SRi
COMB/DFF/TFF/
LATCH/SR*/JK*
*emulated
S/R
IN
BLK CLK
OUT
t
PL
t
BUF
t
EA
t
ER
t
SLW
Q
Central
Switch
Matrix
17466G-025
Figure 15. ispMACH 4A Timing Model
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