參數(shù)資料
型號： ISP1161A
廠商： NXP Semiconductors N.V.
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： 全速通用串行總線的單芯片主機(jī)和設(shè)備控制器
文件頁數(shù)： 93/134頁
文件大?。?/td> 587K
代理商： ISP1161A
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
93 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.1.2
DcAddress register (R/W: B7H/B6H)
This command is used to set the USB assigned address in the DcAddress register
and enable the USB device. The DcAddress register bit allocation is shown in
Table 78
.
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the DcAddress register (accessible by the microcontroller) is not altered
by the bus reset. In response to the standard USB request, Set Address, the firmware
must issue a Write Device Address command, followed by sending an empty packet
to the host. The
new
device address is activated when the host acknowledges the
empty packet.
Code (Hex): B6/B7 —
write/read DcAddress register
Transaction —
write/read 1 word
13.1.3
DcMode register (R/W: B9H/B8H)
This command is used to access the ISP1161A’s DcMode register, which consists of
1 byte (for bit allocation: see
Table 79
). In 16-bit bus mode the upper byte is ignored.
The DcMode register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 —
write/read Mode register
Transaction —
write/read 1 word
Table 77:
Bit
7
DcEndpointConfiguration register: bit description
Symbol
Description
FIFOEN
Logic 1 indicates an enabled FIFO with allocated memory.
Logic 0 indicates a disabled FIFO (no bytes allocated).
EPDIR
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write).
DBLBUF
Logic 1 indicates that this endpoint has double buffering.
FFOISO
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a
bulk or interrupt endpoint.
FFOSZ[3:0]
Selects the FIFO size according to
Table 67
6
5
4
3 to 0
Table 78:
Bit
Symbol
Reset
Access
DcAddress register: bit allocation
7
DEVEN
0
R/W
6
5
4
3
2
1
0
DEVADR[6:0]
0
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 79:
Bit
7
6 to 0
DcAddress register: bit description
Symbol
Description
DEVEN
Logic 1 enables the device.
DEVADR[6:0]
This field specifies the USB device address.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161A1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller
ISP1161A1BD 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161A1BD,118 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BD,151 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BD,157 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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