參數(shù)資料
型號(hào): ISL88550A
廠商: Intersil Corporation
英文描述: Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator
中文描述: 同步降壓控制器,具有采購(gòu)和下沉LDO穩(wěn)壓器
文件頁(yè)數(shù): 7/25頁(yè)
文件大小: 928K
代理商: ISL88550A
7
FN6168.0
October 12, 2005
14
REFIN
External reference input. This is used to regulate the VTT and VTTR outputs to V
REFIN
/2
15
FB
Feedback Input for Buck output. Connect to AV
DD
for a +1.8V fixed output or to GND for a +2.5V fixed
output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive-divider from the output voltage.
FB regulates to +0.7V.
16
OUT
Output Voltage Sense Connection. Connect directly to the positive terminal of the buck capacitors. OUT
senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the Typical
Application Circuit). OUT also serves as the buck output’s feedback input in fixed-output modes. When
discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 20
resistor connected between OUT and ground.
17
VIN
Input Voltage Sense Connection. Connect to input power source. V
IN
is used only to set the PWM on-time
one-shot timer. This pin can range from 2V to 25V.
18
UGATE
High-Side Gate-Driver Output. Swings from PHASE to BOOT. UGATE is low when in shutdown or UVLO.
19
PHASE
External Inductor Connection. Connect PHASE to the input side of the inductor. PHASE is used for both
current limit and the return supply of the UGATE driver.
20
BOOT
Boost Flying-Capacitor Connection. Connect to an external capacitor according to the Typical Application
Circuit (Figure 27). See Boost-Supply Diode and Capacitor Selection (BOOT).
21
LGATE
Synchronous Rectifier Gate-Driver Output. Swings from PGND to V
DD
.
22
VDD
Supply Input for the LGATE Gate Drive. Connect to +4.5V to +5.5V system supply voltage. Bypass to
PGND1 with a 4.7μF ceramic capacitor.
23
PGND1
Power Ground for BUCK controller. Connect PGND1 externally to the underside of the exposed pad.
24
GND
Analog Ground for both BUCK and LDO. Connect externally to the underside of the exposed pad.
25
SKIP#
Pulse-Skipping Control Input. Connect to AV
DD
for low-noise, forced-PWM mode. Connect to GND to
enable pulse-skipping operation.
26
AVDD
Analog Supply for both BUCK and LDO. Bypass to GND with a 1.0μF ceramic capacitor. A 10
internal
resistor is connected between V
DD
and AV
DD
27
SHDNA#
Shutdown Control Input A. Use to control Buck output. A rising edge on SHDNA# clears the overvoltage
and undervoltage protection fault latches (See Table 2 and Table 3). Connect AV
DD
for normal operation.
28
TP0
Test Pin. Must be connected to GND externally
Pin Descriptions
(Continued)
PIN
NAME
FUNCTION
Typical Operating Characteristics
VIN = 12V, VDDQ = 1.8V, TON = GND, SKIP# = AVDD, circuit of Figure 28, T
A
= 25°C, unless otherwise noted.
FIGURE 1. EFFICIENCY vs LOAD - 1.8V (T
ON
= GND)
FIGURE 2. SWITCHING FREQUENCY vs LOAD (TON = GND)
0
10
20
30
40
50
60
70
80
90
100
0.001
0.01
0.1
1
10
LOAD (A)
E
3V
IN
-SKIP
12V
IN
-SKIP
25V
IN
-SKIP
3V
IN
-PWM
12V
IN
-PWM
25V
IN
-PWM
0.001
0.01
0.1
1
10
LOAD (A)
0
100
200
300
400
500
600
700
F
3V
IN
-SKIP
12V
IN
-PWM
25V
IN
-PWM
3V
IN
-PWM
12V
IN
-SKIP
25V
IN
-SKIP
ISL88550A
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