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參數(shù)資料
| 型號： | ISL88550A |
| 廠商： | Intersil Corporation |
| 英文描述： | Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator |
| 中文描述： | 同步降壓控制器，具有采購和下沉LDO穩(wěn)壓器 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 928K |
| 代理商： | ISL88550A |
12
FN6168.0
October 12, 2005
Detailed Description
The ISL88550A combines a synchronous buck PWM
controller, an LDO linear regulator, and a 10mA reference
output. The buck controller drives two external N-Channel
MOSFETs to deliver load currents up to 15A and generates
voltages down to 0.7V from a +2V to +25V input. The LDO
Linear Regulator can source up to 2.5A and sink up to -2.0A
continuously. These features make the ISL88550A ideally
suited for DDR memory application.
The ISL88550A buck regulator is equipped with a fixed
switching frequency up to 600kHz constant on-time PWM
architecture. This control scheme handles wide input/output
voltage ratios with ease, and provides 100ns “instant-on”
response to load transients while maintaining high efficiency
with relatively constant switching frequency.
The buck controller, LDO, and buffered reference output are
provided with independent current limits. Lossless fold-back
current limit in the buck regulator is achieved by monitoring
the drain to source voltage drop of the low side FET. The
ILIM input is used to adjust this current limit. Over-voltage
protection is achieved by latching the low side synchronous
FET on and the high side FET off when the output voltage is
over 116% of its set output. It also features an optional under
voltage protection by latching the MOSFET drivers to the
OFF state during an over current condition when the output
voltage is lower than 70% of the regulated output. Once the
over current condition is removed, the regulator is allowed to
soft-start again. This helps minimize power dissipation
during a short circuit condition.
The current limit in the LDO and buffered reference output is
+3.0A/-2.5A and
±
40mA respectively and neither have the
over or under voltage protection. When the current limit in
either output is reached, the output no longer regulates the
voltage, but will regulate the current to the value of the
current limit.
+5V Bias Supply (V
DD
and AV
DD
)
The ISL88550A requires an external +5V bias supply in
addition to the input voltage (V
IN
). Keeping the bias supply
external to the IC improves the efficiency and eliminates the
cost associated with the +5V linear regulator that would
otherwise be needed to supply the PWM circuit and the gate
drivers. V
DD
, AV
DD
and V
IN
can be connected together if
the input source is a fixed +4.5V to +5.5V supply.
V
DD
is the supply input for the Buck regulator’s MOSFET
drivers, and AV
DD
supplies the power for the rest of the IC.
The current from the AV
DD
and V
DD
power supply must
supply the current for the IC and the gate drive for the
MOSFET’s. This maximim current can be estimated as:
Where I
VDD
, + I
AVDD
are the quiescent supply currents into
V
DD
and AV
DD
and Q
G1
and Q
G2
are the total gate charges
of MOSFETs Q1 and Q2, (at V
GS
= 5V), in the Typical
Application Circuit and
SW
is the switching frequency.
Free-Running Constant-On-Time PWM
The constant on-time PWM control architecture is a pseudo
fixed frequency, constant on-time, current-mode regulator
with voltage feed forward (Figure 21). This architecture relies
on the output filter capacitor’s ESR to act as a current-sense
resistor, so the output ripple voltage provides the PWM ramp
signal. The control algorithm is simple: the high-side switch
on-time is determined solely by a one-shot whose pulse
width is inversely proportional to input voltage and directly
proportional to the output voltage. Another one-shot sets a
minimum off time of 300ns typically. The on-time one-shot is
triggered if the error comparator is low, the low-side switch
current is below the valley current-limit threshold, and the
minimum off-time one-shot has timed out.
ON-Time One Shot (T
ON
)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable one-
shot includes circuitry that varies the on-time in response to
input and output voltages. The high-side switch on-time is
inversely proportional to the input voltage (V
IN
) and is
proportional to the output voltage:
(
2
Q
ON
DS
LOAD
OUT
on
V
where K (the on time scale factor) is set by the T
ON
input
connection (Table 1) and R
DS(ON)Q2
is the on-resistance of
the synchronous rectifier (Q2) in the Typical Application
Circuit. This algorithm results in a nearly constant switching
frequency despite the lack of a fixed-frequency clock
generator. The benefits of a constant switching frequency
are twofold:
1. The frequency can be selected to avoid noise-sensitive
regions such as the 455kHz IF band.
2. The inductor ripple-current operating point remains
relatively constant, resulting in an easy design
methodology and predictable output voltage ripple.
The on-time one-shot has good accuracy at the operating
points specified in the Electrical Characteristics Table
(approximately ±12.5% at 600kHz and 450kHz and ±10% at
200kHz and 300kHz). On-times at operating points far
removed from the conditions specified in the Electrical
Characteristics Table can vary over a wider range. For
example, the 600kHz setting typically runs approximately
10% slower with inputs much greater than 5V due to the very
short on-times required.
The constant on-time translates only roughly to a constant
switching frequency. The on-times guaranteed in the
Electrical Characteristics Table are influenced by resistive
losses and by switching delays in the high-side MOSFET.
Resistive losses, which include the inductor, both MOSFETs,
the output capacitors ESR, and any PC board copper losses
(
)
2
G
1
G
SW
f
AVDD
VDD
BIAS
I
Q
Q
x
I
I
+
+
+
=
(
)
)
IN
R
I
V
K
t
×
+
×
=
ISL88550A
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