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參數(shù)資料
| 型號： | ISL88550A |
| 廠商： | Intersil Corporation |
| 英文描述： | Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator |
| 中文描述： | 同步降壓控制器，具有采購和下沉LDO穩(wěn)壓器 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 928K |
| 代理商： | ISL88550A |
20
FN6168.0
October 12, 2005
Because of the zero-voltage switch operation, the low-side
MOSFET gate-drive loss occurs as a result of charging and
discharging the input capacitance, (C
ISS
). This loss is
distributed among the average LGATE driver’s pull-up and
pull-down resistance, R
LGATE
(1
), and the internal gate
resistance (R
GATE
) of the MOSFET (~2
). The driver power
dissipated is given by:
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses: the channel
conduction loss (P
HSCC
), the VI overlapping switching loss
(P
HSSW
), and the drive loss (P
HSDR
). The high-side
MOSFET does not have body-diode conduction loss
because the diode never conducts current:
Use R
DS(ON)
at T
J(MAX)
.
where I
GATE
is the average UGATE driver output-current
determined by:
where R
UGATE
is the high-side MOSFET driver’s on-
resistance (1.5
typical) and R
GATE
is the internal gate
resistance of the MOSFET (~2
):
where V
GS
= V
DD
= 5V. In addition to the losses above,
allow about 20% more for additional losses because of
MOSFET output capacitances and low-side MOSFET body-
diode reverse recovery charge dissipated in the high-side
MOSFET that is not well defined in the MOSFET data sheet.
Refer to the MOSFET data sheet for thermal-resistance
specifications to calculate the PC board area needed to
maintain the desired maximum operating junction
temperature with the above-calculated power dissipations.
To reduce EMI caused by switching noise, add a 0.1μF
ceramic capacitor from the high-side switch drain to the low-
side switch source, or add resistors in series with UGATE
and LGATE to slow down the switching transitions. Adding
series resistors increases the power dissipation of the
MOSFET, so ensure that this does not overheat the
MOSFET.
MOSFET Snubber Circuit (Buck)
Fast switching transitions cause ringing because of
resonating circuit parasitic inductance and capacitance at
the switching nodes. This high-frequency ringing occurs at
PHASE’s rising and falling transitions and can interfere with
circuit performance and generate EMI. A series R-C snubber
may be added across the lower MOSFET to dampen this
ringing. Below is the procedure for selecting the value of the
series R-C circuit:
1. Connect a scope probe to measure PHASE
to GND, and
observe the ringing frequency,
R
.
2. Find the capacitor value (connected from PHASE to
GND) that reduces the ringing frequency by half.
The circuit parasitic capacitance (C
PAR
) at PHASE is then
equal to 1/3 the value of the added capacitance above. The
circuit parasitic inductance (L
PAR
) is calculated by:
The resistor for critical dampening (R
SNUB
) is equal to 2
π
×
R
x L
PAR
. Adjust the resistor value up or down to tailor the
desired damping and the peak voltage excursion. The
capacitor (C
SNUB
) should be at least 2 to 4 times the value of
the C
PAR
in order to be effective. The power loss of the
snubber circuit (P
RSNUB
) is dissipated in the resistor and can
be calculated as:
where V
IN
is the input voltage and
SW
is the switching
frequency. Choose an R
SNUB
power rating that meets the
specific application’s derating rule for the power dissipation
calculated.
Setting the Current Limit (Buck)
The current-sense method used in the ISL88550A makes
use of the on resistance (R
DS(ON)
) of the low side MOSFET
(Q2 in Typical Application Circuit). When calculating the
current limit, use the worst-case maximum value for
R
DS(ON)
from the MOSFET data sheet, and add some
margin for the rise in R
DS(ON)
with temperature. A good
general rule is to allow 0.5% additional resistance for each
1°C of temperature rise.
The minimum current-limit threshold must be great enough
to support the maximum load current when the current limit
is at the minimum tolerance value. The valley of the inductor
current occurs at I
LOAD(MAX)
minus half the ripple current;
therefore:
where I
LIM(VAL)
equals the minimum valley current-limit
threshold voltage divided by the on resistance of Q2
(R
DS(ON)Q2
). For the 50mV default setting, the minimum
valley current-limit threshold is 40mV. Connect ILIM to AV
DD
for a default 50mV valley current limit threshold. In
adjustable mode, the valley current limit threshold is
precisely 1/10th the voltage seen at ILIM. For an adjustable
threshold, connect a resistive divider from REF to GND with
LGATE
GATE
GATE
R
+
SW
2
GS
ISS
LSDR
P
R
R
f
×
V
C
×
×
=
(
)
ON
DS
2
LOAD
I
IN
OUT
V
HSCC
P
R
V
×
×
=
GATE
I
GD
GS
SW
f
LOAD
I
IN
HSSW
P
Q
Q
V
+
×
×
×
=
(
)
GATE
UGATE
ON
GATE
I
R
R
V
5
+
=
UGATE
GATE
GATE
R
+
SW
GS
G
HSDR
P
R
R
f
V
Q
×
×
×
=
(
)
PAR
C
2
R
f
PAR
2
1
L
×
×
π
=
SW
f
×
2
IN
SNUB
RSNUB
P
V
C
×
=
(
)
(
)
(
)
×
>
2
LIR
I
I
I
MAX
LOAD
MAX
LOAD
VAL
LIM
ISL88550A
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