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參數(shù)資料
| 型號(hào)： | ISL88550A |
| 廠商： | Intersil Corporation |
| 英文描述： | Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator |
| 中文描述： | 同步降壓控制器，具有采購和下沉LDO穩(wěn)壓器 |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 928K |
| 代理商： | ISL88550A |
19
FN6168.0
October 12, 2005
Output Capacitor Selection (Buck)
The output filter capacitor must have low enough equivalent
series resistance (R
ESR
) to meet output ripple and load-
transient requirements, yet have high enough ESR to satisfy
stability requirements. For processor core voltage converters
and other applications in which the output is subject to
violent load transients, the output capacitor’s size depends
on how much R
ESR
is needed to prevent the output from
dipping too low under a load transient. Ignoring the sag due
to finite capacitance:
In applications without large and fast load transients, the
output capacitor’s size often depends on how much R
ESR
is
needed to maintain an acceptable level of output voltage
ripple. The output ripple voltage of a step down controller is
approximately equal to the total inductor ripple current
multiplied by the output capacitor’s R
ESR
. Therefore, the
maximum R
ESR
required to meet ripple specifications is:
The actual capacitance value required relates to the physical
size needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usually
selected by ESR and voltage rating rather than by
capacitance value (this is true of tantalums, OSCONs,
polymers, and other electrolytics).
When using low-capacity filter capacitors, such as ceramic
capacitors, size is usually determined by the capacity
needed to prevent V
SAG
and V
SOAR
from causing problems
during load transients. Generally, once enough capacitance
is added to meet the overshoot requirement, undershoot at
the rising load edge is no longer a problem (see the V
SAG
and V
SOAR
equations in the Transient Response section).
VTT Output Cap Selection (LDO)
Place 2 x 10μF 0805 ceramic capacitor as close to VTT
output as possible for optimum performance of output
loading up to +2.5A/-2.0A. In most applications, it is not
necessary to add more capacitance. However, optional
additional capacitances can be added further away (>1.5in)
from VTT output.
VTTR Output Cap Selection (LDO)
The VTTR buffer is a scaled down version of the VTT
regulator, with much smaller output transconductance. Its
compensation cap can therefore be smaller, and its ESR
larger, than what is required for its larger counterpart. For
typical applications requiring load current up to ±20mA, a
ceramic cap with a minimum value of 1μF is recommended
(ESR<0.3
). Tie this cap between VTTR and analog ground
plane.
VTTI Input Cap Selection (LDO)
Both the VTT and VTTR output stages are powered from the
same VTTI input. Their output voltages are referenced to the
same REFIN input. The value of the VTTI bypass cap is
chosen to limit the amount of ripple/noise at VTTI, or the
amount of voltage dip during a load transient. Typically, a
ceramic cap of at least 10μF should be used. This value is to
be increased with larger load current, or if the trace from the
VTTI pin to the power source is long and has significant
impedance. Furthermore, to prevent undesirable
VTTI bounce from coupling back to the REFIN input and
possibly causing instability in the loop, the REFIN pin should
ideally tap its signal from a separate low impedance DC
source rather than directly to the VTTI input. If the latter is
unavoidable, increase the amount of bypass at the VTTI
input and add additional bypass at the REFIN pin.
MOSFET Selection (Buck)
The ISL88550A drive external, logic-level, N-Channel
MOSFETs as the circuit-switch elements. The key selection
parameters:
Maximum Drain-To-Source Voltage (V
DSS
):
should be at
least 20% higher than input supply rail at the high side
MOSFET’s drain.
Choose the MOSFETs with rated R
DS(ON)
at V
GS
= 4.5V.
For a good compromise between efficiency and cost, choose
the high-side MOSFET that has a conduction loss equal to
switching loss at nominal input voltage and maximum output
current (see below). For low-side MOSFET, make sure that it
does not spuriously turn on because of dV/dt caused by
high-side MOSFET turning on, as this would result in shoot
through current degrading the efficiency. MOSFETs with a
lower Q
GD
to Q
GS
ratio have higher immunity to dV/dt.
For proper thermal-management design, calculate the power
dissipation at the desired maximum operating junction
temperature, maximum output current, and worst-case input
voltage (for low-side MOSFET, worst case is at V
IN(MAX)
; for
high-side MOSFET, it could be either at V
IN(MIN)
or
V
IN(MAX)
). The high-side MOSFET and low-side MOSFET
have different loss components due to the circuit operation.
The low-side MOSFET operates as a zero voltage switch;
therefore, major losses are
1. The channel conduction loss (P
LSCC
)
2. The body diode conduction loss (P
LSDC
)
3. The gate-drive loss (P
LSDR
)
where V
F
is the body-diode forward-voltage drop,
t
DT
is the
dead time (
≈
30ns), and
f
SW
is the switching frequency.
(
)
MAX
LOAD
I
STEP
V
ESR
R
≤
(
)
LIR
I
V
R
MAX
LOAD
RIPPLE
ESR
×
≤
(
)
ON
DS
2
LOAD
I
IN
OUT
V
LSCC
P
R
V
1
×
×
=
SW
DT
F
LOAD
I
LSDC
P
f
t
V
×
×
×
=
ISL88550A
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