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參數(shù)資料
| 型號(hào)： | ISL6539IAZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Wide Input Range Dual PWM Controller with DDR Option |
| 中文描述： | DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QSOP-28 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 503K |
| 代理商： | ISL6539IAZ-T |
5
FN9144.4
June 6, 2005
Functional Pin Description
GND (Pin 1, 9, 20)
Signal ground for the IC. All three ground pins must be
connected to ground for proper IC operation. Connect to the
ground plane through a path as low in inductance as
possible.
LGATE1, LGATE2 (Pin 2, 27)
Connect these pins to the gates of the corresponding lower
MOSFETs. These pins provide the PWM-controlled gate
drive for the lower MOSFETs.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters. These pins must
be connected to the ground plane through a path as low in
inductance as possible.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
Connect these pins to the gates of the corresponding upper
MOSFETs. These pins provide the PWM-controlled gate
drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect these pins to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. The anode
of the bootstrap diode is connected to the VCC voltage.
PWM CONVERTERS
Load Regulation
0.0mA < I
VOUT1
< 5.0A; 5.0V < V
IN
< 15.0V
-2.0
-
+2.0
%
VSEN pin bias current
I
VSEN
By design
-
80
-
nA
Minimum Duty Cycle
D
MIN
-
4
-
%
Maximum Duty Cycle
D
MAX
-
87
-
%
Undervoltage Shut-Down Level
V
UVL
Fraction of the set point; ~2ms noise filter
70
75
80
%
Overvoltage Protection
V
OVP1
Fraction of the set point; ~2ms noise filter
110
115
-
%
GATE DRIVERS
Upper Drive Pull-Up Resistance
R
2UGPUP
V
CC
= 5V
-
4
8
Upper Drive Pull-Down Resistance
R
2UGPDN
V
CC
= 5V
-
2.3
4
Lower Drive Pull-Up Resistance
R
2LGPUP
V
CC
= 5V
-
4
8
Lower Drive Pull-Down Resistance
R
2LGPDN
V
CC
= 5V
-
1.1
3
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
V
PG-
Fraction of the set point; ~3ms noise filter
84
89
92
%
Power Good Higher Threshold
V
PG+
Fraction of the set point; ~3ms noise filter.
110
115
120
%
PGOODx Leakage Current
I
PGLKG
V
PULLUP
= 5.5V
-
-
1
μ
A
PGOODx Voltage Low
V
PGOOD
I
PGOOD
= -4mA
-
0.5
1
V
ISEN sourcing current
By design
-
-
260
μ
A
OCSET sourcing current range
2
-
20
μ
A
EN - Low (Off)
-
-
0.8
V
EN - High (On)
2.0
-
-
V
DDR - Low (Off)
-
-
0.8
V
DDR - High (On)
3
-
-
V
DDR REF Output Voltage
V
DDREF
DDR = 1, I
REF
= 0...10mA
0.99*
V
OC2
V
OC2
1.01*
V
OC2
V
DDR REF Output Current
I
DDREF
DDR = 1. Guaranteed by design.
-
10
12
mA
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6539
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