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參數(shù)資料
| 型號(hào)： | ISL6539IAZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Wide Input Range Dual PWM Controller with DDR Option |
| 中文描述： | DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QSOP-28 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 503K |
| 代理商： | ISL6539IAZ-T |
10
FN9144.4
June 6, 2005
Current Sensing
The current on the lower MOSFET is sensed by measuring
its voltage drop within its on-time. In order to activate the
current sampling circuitry, two conditions need to be met. (1)
the LGATE is high and (2) the phase pin sees a negative
voltage for regular buck operation, which means the current
is freewheeling through lower MOSFET. For the second
channel of the DDR application, the phase pin voltage needs
to be higher than 0.1V to activate the current sensing circuit
for bidirectional current sensing. The current sampling
finishes at about 400ns after the lower MOSFET has turned
on. This current information is held for current mode control
and overcurrent protection. The current sensing pin can
source up to 260μA. The current sense resistor and OCSET
resistor can be adjusted simultaneously for the same
overcurrent protection level; however, the current sensing
gain will be changed only according to the current sense
resistor value, which will affect the current feedback loop
gain. The middle point of the ISEN current can be at 75μA,
but it can be tuned up and down to fit application needs.
If another channel is switching at the moment the current
sample is finishing, it could cause current sensing error and
phase voltage jitter. In the design stage, the duty cycles and
synchronization have to be analyzed for all the input voltage
and load conditions to reduce the chance of current sensing
error. The relationship between the sampled current and
MOSFET current is given by:
Which means the current sensing pin will source current to
make the voltage drop on the MOSFET equal to the voltage
generated on the sensing resistor, plus the internal resistor,
along the ISEN pin current flowing path.
Feedback Loop Compensation
Both channel PWM controllers have internally compensated
error amplifiers. To make internal compensation possible
several design measures were taken.
The ramp signal applied to the PWM comparator has been
made proportional to the input voltage by the VIN pin. This
keeps the product of the modulator gain and the input
voltage constant even when the input voltage varies.
The load current proportional signal is derived from the
voltage drop across the lower MOSFET during the PWM
off time interval, and is subtracted from the error amplifier
output signal before the PWM comparator input. This
effectively creates an internal current control loop.
The resistor connected to the ISEN pin sets the gain in the
current sensing. The following expression estimates the
required value of the current sense resistor, depending on
the maximum continuous load current, and the value of the
MOSFETs r
DSON
, assuming the ISEN pin sources 75μA
current.
Because the current sensing circuit is a sample-and-hold
type, the information obtained at the last moment of the
sampling is being used. This current sensing circuit samples
the inductor current very close to its peak value. The current
feedback essentially injects a resistor R
i
in series with the
original LC filter as shown in Figure 5, where the sample-
and-hold effect of the current loop has been ignored. Vc and
Vo are small signal components extracted from its DC
operation points.
The value of the injected resistor can be estimated by:
R
i
is in k
,
and R
DS
and R
CS
are in
. V
in
divided by V
ramp
,
is defined as Gm, which is a constant 8 or 18dB for both
channels in dual switcher applications, when Vin is above
3V. Refer to Tables 1 and 2 for the ramp amplitude in
different Vin pin connections. The feed-forward effect of the
Vin is reflected in Gm. V
c
is defined as the error amplifier
output voltage.
R2
R1
UGA
T
E
ISEN
LGA
T
E
ISL6539
L1
Q1
Q2
C1
VOUT
VSEN
OCSET
V
i
n
R
CS
R
OC
Cz
FIGURE 4. THE INTERNAL COMPENSATOR
I
SEN
R
CS
140
+
(
)
r
DS ON
)
I
D
=
R
CS
I
--------------------------------------------
R
75
A
)
=
140
–
FIGURE 5. THE EQUIVALENT CIRCUIT OF THE POWER
STAGE WITH CURRENT LOOP INCLUDED
+
Gm*Vc
Ri
Lo
DCR
Co
Ro
Vo
ESR
+
-
R
i
V
ramp
----------------
r
CS
)
------------+
4.4k
=
ISL6539
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