參數(shù)資料
型號(hào)： ISL6539IAZ-T
廠商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： Wide Input Range Dual PWM Controller with DDR Option
中文描述： DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28
封裝： ROHS COMPLIANT, PLASTIC, QSOP-28
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 503K
代理商： ISL6539IAZ-T
14
FN9144.4
June 6, 2005
For the VTT channel where output is derived from the VDDQ
output, some control and protective functions have been
significantly simplified. For example, the overcurrent, and
overvoltage, and undervoltage protections for the second
channel controller are disabled when the DDR pin is set
high. As the VTT channel tracks the VDDQ/2 voltage, the
soft-start function is not required, and the SOFT2 pin may be
left open, in the event both channels are enabled
simultaneously. However, if the VTT channel is enabled later
than the VDDQ, the SOFT2 pin must have a capacitor in
place to ensure soft-start. In case of overcurrent or
undervoltage caused by short circuit on VTT, the fault current
will propagate to the first channel and shut down the
converter.
The VREF voltage will be present even if the VTT is
disabled.
Channel Synchronization in DDR Applications
The presence of two PWM controllers on the same die
requires channel synchronization, to reduce inter-channel
interference that may cause the duty factor jitter and
increased output ripple.
The PWM controller is at greatest noise susceptibility when
an error signal on the input of the PWM comparator
approaches the decision-making point. False triggering may
occur, causing jitter and affecting the output regulation.
A common approach used to synchronize dual channel
converters is out-of-phase operation. Out-of-phase
operation reduces input current ripple and provides a
minimum interference for channels that control different
voltage levels.
When used in a DDR application with cascaded converters
(VTT generated from VDDQ), several methods of
synchronization are implemented in the ISL6539. When the
DDR pin is connected to GND for dual switcher applications,
the channels operate 180° out-of-phase. In the DDR mode,
when the DDR pin is connected to VCC, the channels
operate either with 0° phase shift, when the VIN pin is
connected to the GND, or with 90° phase shift if the VIN pin
is connected to a voltage higher than 4.2V.
The following table lists the different synchronization
schemes and their usage:
Application Information
Design Procedures
GENERAL
A ceramic decoupling capacitor should be used between the
VCC and GND pin of the chip. There are three major
currents drawn from the decoupling capacitor:
1. the quiescent current, supporting the internal logic and
normal operation of the IC
2. the gate driver current for the lower MOSFETs
3. and the current going through the external diodes to the
bootstrap capacitor for upper MOSFET.
In order to reduce the noisy effect of the bootstrap capacitor
current to the IC, a small resistor, such as 10
, can be used
with the decoupling cap to construct a low pass filter for the
IC, as shown in Figure 9.
The soft-start capacitor and the resistor divider setting the
output voltage is easy to select as discussed in the “Block
Diagram” on page 8.
Selection of the Current Sense Resistor
The value of the current sense resistor determines the gain
of the current sensing circuit. It affects the current loop gain
and the overcurrent protection setpoint. The voltage drop on
the lower MOSFET is sensed within 400ns after the upper
MOSFET is turned off. The current sense pin has a 140
resistor in series with the external current sensing resistor.
The current sense pin can source up to a 260μA current
while sensing current on the lower MOSFET, in such a way
that the voltage drop on the current sensing path would
equal to the voltage on the MOSFET.
I
D
can be assumed to be the inductor peak current. In a
worst case scenario, the high temperature r
DSON
could
increase to 150% of the room temperature level. During
overload condition, the MOSFET drain current I
D
could be
130% higher than the normal inductor peak. If the inductor
has 30% peak-to-peak ripple, I
D
would equal to 115% of the
load current. The design should consider the above factors
so that the maximum I
SOURCING
will not saturate to 260μA
under worst case conditions. To be safe, I
SOURCING
should
be less than 100μA in normal operation at room
temperature. The formula in the earlier discussion assumes
DDR PIN
VIN PIN
SYNCHRONIZATION
0
Vin pin >4.2V
180°
out of phase
1
Vin pin voltage <4.2V
0° phase
1
Vin pin voltage >4.1V
90° phase shift
10
VCC
TO BOOT
5V
FIGURE 9. INPUT FILTERING FOR THE CHIP
I
SOURCING
140
R
CS
+
(
)
I
D
r
DS ON
)
=
ISL6539
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