- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384525 > ISL6539IAZ-T (INTERSIL CORP) Wide Input Range Dual PWM Controller with DDR Option PDF資料下載
參數(shù)資料
| 型號： | ISL6539IAZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Wide Input Range Dual PWM Controller with DDR Option |
| 中文描述： | DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QSOP-28 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 503K |
| 代理商： | ISL6539IAZ-T |
17
FN9144.4
June 6, 2005
Specification Table on page 4. For example, if the gate driver
turn-on path MOSFET has a typical on-resistance of 4
, its
maximum turn-on current is 1.2A with 5V Vcc. This current
would decay as the gate voltage increased. With the
assumption of linear current decay, the turn-on time of the
MOSFETs can be written with:
Q
gd
is used because when the MOSFET drain-to-source
voltage has fallen to zero, it gets charged. Similarly, the turn-
off time can be estimated based on the gate charge and the
gate drivers sinking current capability.
The total power loss of the upper MOSFET is the sum of the
switching loss and the conduction loss. The temperature rise
on the MOSFET can be calculated based on the thermal
impedance given on the datasheet of the MOSFET. If the
temperature rise is too much, a different MOSFET package
size, layout copper size, and other options have to be
considered to keep the MOSFET cool. The temperature rise
can be calculated by:
The MOSFET gate driver loss can be calculated with the
total gate charge and the driver voltage Vcc. The lower
MOSFET only charges the miller capacitor at turn-off.
Based on the above calculation, the system efficiency can
be estimated by the designer.
Confining the Negative Phase Node Voltage Swing
with Schottky Diode
At each switching cycle, the body diode of the lower
MOSFET will conduct before the MOSFET is turned-on, as
the inductor current is flowing to the output capacitor. This
will result in a negative voltage on the phase node. The
higher the load current, the lower this negative voltage. This
voltage will ring back less negative when the lower MOSFET
is turned on.
A total 400ns period is given to the current sample-and-hold
circuit on the ISEN pin to sense the current going through
the lower MOSFET after the upper MOSFET turns off. An
excessive negative voltage on the lower MOSFET will be
treated as overcurrent. In order to confine this voltage, a
schottky diode can be used in parallel with the lower
MOSFET for high load current applications. PCB layout
parasitics should be reduced in order to reduce the negative
ringing of phase voltage.
The second concern for the phase node voltage going into
negative is that the boot strap capacitor between the BOOT
and PHASE pin could get be charged higher than VCC
voltage, exceeding the 6.5V absolute maximum voltage
between BOOT and PHASE when the phase became
negative. A resistor can be placed between the cathode of
the boot strap diode and BOOT pin to increase the charging
time constant of the boot cap. This resistor will not affect the
turn-on and off of the upper MOSFET.
A schottky diode can reduce the reverse recovery of the lower
MOSFET when transitioning from freewheeling to blocking,
therefore, it is generally good practice to have a schottky
diode closely parallel with the lower MOSFET. B340LA, from
Diodes, Inc., can be used as the external schottky diode.
Tuning the Turn-on of Upper MOSFET
The turn-on speed of the upper MOSFET can be adjusted by
the resistor connecting the boot cap to the boot pin of the chip.
This resistor can confine the voltage ringing on the boot
capacitor from coupling to the boot pin. This resistor slows
down only the turn-on of the upper MOSFET. If the upper
MOSFET is turned on very fast, it could result in a very high
dv/dt on the phase node, which could couple into the lower
MOSFET gate through the miller capacitor, causing
momentous shoot-through. This phenomenon, together with
the reverse recovery of the body diode of the lower MOSFET,
can overshoot the phase node voltage to beyond the voltage
rating of the MOSFET. However, a bigger resistor will slow the
turn-on of the MOSFET too much and lower the efficiency.
Trade-offs need to be made in choosing such a resistor.
System Loop Gain and Stability
The system loop gain is a product of three transfer functions:
1. the transfer function from the output voltage to the
feedback point,
2. the transfer function of the internal compensation circuit
from the feedback point to the error amplifier output
voltage,
3. and the transfer function from the error amplifier output to
the converter output voltage.
These transfer functions are written in a closed form in the
Theory of Operation
section. The external capacitor, in
parallel with the upper resistor of the resistor divider, Cz, can
be used to tune the loop gain and phase margin. Other
component parameters, such as the inductor value, can be
changed for a wider cross-over frequency of the system loop
gain. A body plot of the loop gain transfer function with a 45
degree phase margin (a 60 degree phase margin is better) is
desirable to cover component parameter variations.
Testing the Overvoltage on Buck Converters
For synchronous buck converters, if an active source is used
to raise the output voltage for the overvoltage protection test,
the buck converter will behave like a boost converter and
dump energy from the external source to the input. The
overvoltage test can be done on ISL6539 by connecting the
VSEN pin to an external voltage source or signal generator
through a diode. When the external voltage, or signal
generator voltage, is tuned to a higher level than the
overvoltage threshold (the lower MOSFET will be on), it
T
on
2Q
I
driver
----------------
=
T
rise
θ
ja totalpower loss
=
P
driver
V
cc
Q
gs
F
sw
=
ISL6539
相關PDF資料 |
PDF描述 |
|---|---|
| ISL6540 | Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability |
| ISL6540_06 | Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability |
| ISL6540CRZ | Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability |
| ISL6540CRZA | Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability |
| ISL6540IRZ | Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6540ACRZ | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:75 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:1MHz 占空比:81% 電源電壓:4.3 V ~ 13.5 V 降壓:是 升壓:是 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:0°C ~ 70°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:管件 產品目錄頁面:1051 (CN2011-ZH PDF) 其它名稱:296-2543-5 |
| ISL6540ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 特色產品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 標準包裝:1 系列:PowerWise® PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1MHz 占空比:81% 電源電壓:4.5 V ~ 18 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-5°C ~ 125°C 封裝/外殼:32-WFQFN 裸露焊盤 包裝:Digi-Reel® 產品目錄頁面:1303 (CN2011-ZH PDF) 其它名稱:LM3754SQDKR |
| ISL6540ACRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6540ACRZ-T W/GOLD BOND WIRE ONLY - Tape and Reel |
| ISL6540AIRZ | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6540AIRZA | 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復。