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參數(shù)資料
| 型號： | ISL6532 |
| 廠商： | Intersil Corporation |
| 英文描述： | ACPI Regulator/Controller for Dual Channel DDR Memory Systems |
| 中文描述： | ACPI的穩(wěn)壓器/雙通道DDR內(nèi)存控制器系統(tǒng) |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 365K |
| 代理商： | ISL6532 |
8
the ISL6532 starts an internal counter. Following a cold start
or any subsequent S5 state, state transitions are ignored
until the system enters S0/S1. None of the regulators will
begin the soft start procedure until the 5V Standby bus has
exceeded POR, the 12V bus has exceeded POR and V
NCH
has exceeded the trip level.
Once all of these conditions are met, the PWM error
amplifier will first be reset by internally shorting the COMP
pin to the FB pin. This reset lasts for 2048 clock cycles which
is typically 8.2ms (one clock cycle = 1/f
OSC
). The digital soft
start sequence will then begin.
The PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). The
internal V
TT
LDO will also soft start through the reference that
tracks the output of the PWM regulator. The soft start lasts for
2048 clock cycles, which is typically 8.2ms. This method
provides a rapid and controlled output voltage rise.
Figure 1 shows the soft start sequence for a typical cold
start. Due to the soft start capacitance, C
SS
, on the
VREF_IN pin, the S5 to S0 transition profile of the V
TT
rail
will have a more rounded features at the start and end of the
soft start whereas the V
DDQ
profile has distinct starting and
ending points to the ramp up.
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals, the ISL6532 can achieve PGOOD status
significantly faster than other devices that depend on the
Latched_Backfeed_Cut signal for timing.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532 will disable the V
TT
linear regulator. The V
DDQ
standby regulator will be enabled and the V
DDQ
switching
regulator will be disabled. NCH is pulled low to disable the
backfeed blocking MOSFET. PGOOD will also transition
LOW. When V
TT
is disabled, the internal reference for the
V
TT
regulator is internally shorted to the V
TT
rail. This allows
the V
TT
rail to float. When floating, the voltage on the V
TT
rail will depend on the leakage characteristics of the memory
and MCH I/O pins. It is important to note that the V
TT
rail
may not bleed down to 0V.
The V
DDQ
rail will be supported in the S3 state through the
standby V
DDQ
LDO. When S3 transitions LOW, the Standby
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut
off time will range between 4 and 8μs. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail
through the P5VSBY pin. It is recommended that the 5V
Standby rail be used as the current delivery capability of the
LDO is greater.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the ISL6532
will enable the V
DDQ
switching regulator, disable the V
DDQ
standby regulator, enable the V
TT
LDO and force the NCH
pin to a high impedance state turning on the blocking
MOSFET. The internal short between the V
TT
reference and
the V
TT
rail is released. Upon release of the short, the
capacitor on VREF_IN is then charged up through the
internal resistor divider network. The V
TT
output will follow
this capacitor charge-up, acting as the S3 to S0 transition
soft start for the V
TT
rail. The PGOOD comparator is
enabled only after 2048 clock cycles, or typically 8.2ms, have
passed following the S3 transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
should be noted that the soft start profile of the V
TT
LDO
output will vary according to the value of the capacitor on the
VREF_IN pin.
FIGURE 1. TYPICAL COLD START
V
TT
V
DDQ
500mV/DIV
12VATX 2V/DIV
5VSBY
1V/DIV
S3
S5
500mV/DIV
PGOOD
5V/DIV
12V POR
SOFT START
INITIATES
SOFT START ENDS
PGOOD COMPARATOR
ENABLED
2048 CLOCK
CYCLES
2048 CLOCK
CYCLES
FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION
V
TT
V
DDQ
500mV/DIV
12VATX 2V/DIV
S3
S5
500mV/DIV
PGOOD
5V/DIV
12V POR
PGOOD COMPARATOR
ENABLED
2048 CLOCK
CYCLES
V
T
ISL6532
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