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參數(shù)資料
| 型號(hào)： | ISL6532 |
| 廠商： | Intersil Corporation |
| 英文描述： | ACPI Regulator/Controller for Dual Channel DDR Memory Systems |
| 中文描述： | ACPI的穩(wěn)壓器/雙通道DDR內(nèi)存控制器系統(tǒng) |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 365K |
| 代理商： | ISL6532 |
10
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal V
TT
LDO,
the ground pad, pin 21, should be connected to the internal
ground plane through at least four vias. This allows the heat
to move away from the IC and also ties the pad to the ground
plane through a low impedance path.
The switching components should be placed close to the
ISL6532 first. Minimize the length of the connections
between the input capacitors, C
IN
, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
error amplifier output (V
E/A
) is compared with the oscillator
(OSC) triangular wave to provide a pulse-width modulated
(PWM) wave with an amplitude of V
IN
at the PHASE node.
The PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
V
DDQ
5VSBY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
L
OUT
C
OUT1
C
IN
V
IN_DDR
KEY
COMP
ISL6532
UGATE
R
4
R
2
C
BP
FB
GND
5VSBY
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
R
1
C
2
VIA CONNECTION TO GROUND PLANE
L
Q
1
R
3
C
3
C
1
Q
2
12V
ATX
C
BP
GND
P12V
LGATE
P5VSBY
VDDQ(2)
VTT(2)
C
OUT2
L
V
DDQ
V
TT
NCH
GND PAD
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
V
DDQ
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
DDQ
FB
Z
FB
ISL6532
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
R
4
V
DDQ
0.8
1
R
1
R
4
------
+
×
=
ISL6532
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