參數(shù)資料
型號： ISL51002CQZ-110
廠商： Intersil
文件頁數(shù)： 7/33頁
文件大小： 0K
描述： IC FRONT END 10BIT VID 128-MQFP
標(biāo)準(zhǔn)包裝： 66
位數(shù)： 10
通道數(shù)： 3
功率（瓦特）： 1.2W
電壓 - 電源，模擬： 1.8V，3.3V
電壓 - 電源，數(shù)字： 1.8V，3.3V
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
15
FN6164.3
February 29, 2012
0x19
Red Offset LSB, (0x00)
5:0
N/A
7:6
Red Offset LSB
2 LSBs of 10-bit offset word
0x1A
Green Offset MSB, (0x80)
7:0
Green Offset MSB
ABLC off: upper 8-bits to Green offset DAC
ABLC enabled: Green digital offset
(See Red Offset)
0x1B
Green Offset LSB, (0x00)
5:0
N/A
7:6
Green Offset LSB
See Red Offset
0x1C
Blue Offset MSB, (0x80)
7:0
Blue Offset MSB
ABLC off: upper 8-bits to Blue offset DAC
ABLC enabled: Blue digital offset
(See Red Offset)
0x1D
Blue Offset LSB, (0x00)
5:0
N/A
7:6
Blue Offset LSB
See Red Offset
0x1E
PLL Htotal MSB, (0x06)
5:0
PLL Htotal MSB
14-bit HTOTAL. PLL updated on LSB write only.
0x1F
PLL Htotal LSB, (0x98)
7:0
PLL Htotal LSB
PLL updated on LSB write only. SXGA default
0x20
PLL Phase, (0x00)
5:0
PLL Sampling Phase
Used to control the phase of the ADC’s sample point relative
to the period of a pixel. Adjust to obtain optimum image quality.
One step = 5.625° (1.56% of pixel period).
0x21
PLL Pre-coast, (0x04)
7:0
Pre-coast
Number of lines the PLL will coast prior to the start of VSYNC.
0x22
PLL Post-coast, (0x04)
7:0
Post-coast
Number of lines the PLL will coast after the end of VSYNC.
0x23
PLL Misc, (0x00)
0
PLL Lock Edge HSYNC
0: PLL locks to trailing edge of selected HSYNC (default)
1: PLL locks to leading edge of selected HSYNC
1
CLKINV ENABLE
0: CLKINV input ignored
1: CLKINV input enabled
2
Ext Coast SEL
0: Internal COAST generation
1: External COAST source
3
Ext Coast POL
0: Active high external COAST
1: Active low external COAST
4
EXT CLOCK
0: Internal pixel clock from DPLL
1: External pixel clock from EXTCLKin pin
0x24
DC Restore and ABLC
starting pixel MSB, (0x00)
5:0
DC Restore and ABLC
starting pixel (MSB)
Pixel after Raw HSYNC trailing edge to begin DC restore and
ABLC. 14-bits.
0x25
DC Restore and ABLC
starting pixel LSB, (0x02)
7:0
DC Restore and ABLC
starting pixel (LSB)
0x26
DC Restore Clamp Width,
(0x10)
7:0
DC Restore clamp width
Only applies to DC restore clamp used for AC-coupled
configurations. A value of 0x00 means the clamp DAC is never
connected to the input.
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
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