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參數(shù)資料
| 型號(hào)： | ISL51002CQZ-110 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/33頁 |
| 文件大小： | 0K |
| 描述： | IC FRONT END 10BIT VID 128-MQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.2W |
| 電壓 - 電源，模擬： | 1.8V，3.3V |
| 電壓 - 電源，數(shù)字： | 1.8V，3.3V |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
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24
FN6164.3
February 29, 2012
The offset controls shift the entire RGB input range, changing
the input image brightness. Three separate registers provide
independent control of the R, G, and B channels. Their
nominal setting is 0x8000, which forces the ADC to output
code 0x0000 (or 0x200 for the R (Pr) and B (Pb) channels in
YPbPr mode) during the back porch period when ABLC is
enabled.
Functional Description
Inputs
The ISL51002 digitizes analog video inputs in both RGB
and Component (YPbPr) formats, with or without
embedded sync (SOG).
RGB Inputs
For RGB inputs, the black/blank levels are identical and equal
to 0V. The range for each color is typically 0V to 0.7V from
black to white. HSYNC and VSYNC are separate signals.
Component YPbPr Inputs
In addition to RGB and RGB with SOG, the ISL51002 has an
option that is compatible with the component YPbPr video
inputs typically generated by DVD players. While the
ISL51002 digitizes signals in these color spaces, it can only
perform color space conversion from RGB to YUV; if it
digitizes an RGB signal, it outputs digital RGB or YUV, while
if it digitizes a YPbPr signal, it outputs digital YCbCr, also
called YUV.
The Luminance (Y) signal is applied to the Green Channel
and is processed in a manner identical to the Green input
with SOG described previously. The color difference signals
Pb and Pr are bipolar and swing both above and below the
black level. When the YPbPr mode is enabled, the black
level output for the color difference channels shifts to a mid
scale value of 0x200. Setting configuration register
0x10[4] = 1 enables the YPbPr signal processing mode of
operation.
The ISL51002 can optionally decimate the incoming data to
provide a 4:2:2 output stream (configuration register
0x28[0] = 1) as shown in Table 2.
RGB to YUV Color Space Converter (CSC)
For RGB inputs, the internal Color Space Converter, when
enabled (register 0x28-bit [6] = 1), will convert from the RGB
color space to the YUV (YCbCr) color space using the
following conversion formulas:
Y = 0.299R + 0.587G + 0.114B
U = -0.172R - 0.339G + 0.511B + 512
V = 0.511R - 0.428G - 0.083B + 512
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled
(See register 0x10[3]). AC coupling is usually preferred since
it allows video signals with substantial DC offsets to be
accurately digitized. The ISL51002 provides a complete
internal DC-restore function, including the DC restore clamp
(See Figure 1) and programmable clamp timing (registers
0x24, 0x25, and 0x26).
When AC-coupled, the DC restore clamp is applied every
line, a programmable number of pixels after the trailing edge
of HSYNC. If register 0x60[2] = 0 (the default), the clamp will
not be applied while the DPLL is coasting, preventing any
clamp voltage errors from composite sync edges,
equalization pulses, or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC
Restore and ABLC Starting Pixel registers (0x24 and
0x25) has been reached. The clamp is applied for the
number of pixels specified by the DC Restore Clamp Width
Register (0x26). The clamp can be applied to the back porch
of the video, or to the front porch (by increasing the DC
Restore and ABLC Starting Pixel registers so all the active
video pixels are skipped).
Note: The TriLevel detect for Sync on Green (SOG) utilizes
the digitized data from the selected Green video channel. If
TriLevel Sync is present, the default DC Clamp start position
will clamp at the top of the TriLevel Sync pulse giving a false
negative for TriLevel detect and clamping off the bottom half
of the green video. If you have an indication of active SOG
you must move the clamp start to a value greater than 0x30
to check to see if the Tri-level Sync is present.
If DC-coupled operation is desired, the input to the ADC will be
the difference between the input signal (RIN1, for example) and
that channel’s ground reference (RGBGND1 in that example).
TABLE 1. YUV MAPPING (4:4:4)
INPUT
SIGNAL
ISL51002
INPUT
CHANNEL
ISL51002
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Y0Y1Y2Y3
Pb
Blue
U0U1U2U3
Pr
Red
V0V1V2V3
TABLE 2. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL51002
INPUT
CHANNEL
ISL51002
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Y0Y1Y2Y3
Pb
Blue
Driven Low
Pr
Red
U0V0U2V2
ISL51002
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| ISL51002CQZ-150 | 制造商:Intersil Corporation 功能描述:AFE VID 3ADC 10-BIT 1.8V/3.3V 128MQFP EP - Trays 制造商:Intersil 功能描述:10 BIT VID AFE MEASURE&AUTO-ADJUST 制造商:Intersil Corporation 功能描述:10-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features |
| ISL51002CQZ-165 | 功能描述:IC FRONT END 10BIT VID 128-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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