參數(shù)資料
型號(hào)： ISL51002CQZ-110
廠商： Intersil
文件頁(yè)數(shù)： 11/33頁(yè)
文件大小： 0K
描述： IC FRONT END 10BIT VID 128-MQFP
標(biāo)準(zhǔn)包裝： 66
位數(shù)： 10
通道數(shù)： 3
功率（瓦特）： 1.2W
電壓 - 電源，模擬： 1.8V，3.3V
電壓 - 電源，數(shù)字： 1.8V，3.3V
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤
19
FN6164.3
February 29, 2012
0x31
HSYNC/SOG Config,
(0x04)
3:0
Glitch Filter Width
0: 16 crystal clocks
1: 17 crystal clocks
2: 1 crystal clocks
3: 2 crystal clocks
4: 3 crystal clocks (default)
5: 4 crystal clocks
6: 5 crystal clocks
7: 6 crystal clocks
8: 7 crystal clocks
9: 8 crystal clocks
10: 9 crystal clocks
11: 10 crystal clocks
12: 11crystal clocks
13: 12 crystal clocks
14: 13 crystal clocks
15: 14 crystal clocks
4
Sync Glitch Filter Disable
0: glitch filter enabled
1: glitch filter disabled
5
SOG Hyst Disable
0: 40mV hysteresis enabled
1: 40mV hysteresis disabled
6
SOG LPF Disable
0: 14MHz SOG Low Pass Filter Enabled
1: 14MHz SOG Low Pass Filter Disabled
0x32
Sync Polling Control, (0x00)
0
CH0 Polling
0: Enable
1: Disable
1
CH1 Polling
0: Enable
1: Disable
2
CH2 Polling
0: Enable
1: Disable
3
Reserved
Set to 1 when writing, ignore when reading
4
CH0 Connector Type
0: RGB DB15 (poll for HSYNC, CSYNC, and SOG)
1: Component (poll for SOG only)
5
CH1 Connector Type
0: RGB DB15 (poll for HSYNC, CSYNC, and SOG)
1: Component (poll for SOG only)
6
CH2 Connector Type
0: RGB DB15 (poll for HSYNC, CSYNC, and SOG)
1: Component (poll for SOG only)
7
Reserved
Set to 0 when writing, ignore when reading
MEASUREMENT REGISTERS
0x40
HSYNC Period MSB,
(read only)
7:0
HSYNC Period MSB
These registers report a 16-bit value containing the number of
crystal clocks inside a 16 consecutive HSYNC period window.
This means the 16-bit number will reflect one HSYNC period
with 1/16 LSB resolution - the last 4-bits of the measurement
will be fractional.
0x41
HSYNC Period LSB,
(read only)
7:0
HSYNC Period LSB
0x42
HSYNC Width MSB,
(read only)
7:0
HSYNC Width MSB
These registers report a 16-bit value containing the number of
crystal clocks inside 16 consecutive HSYNC pulses. This
means the 16-bit number will reflect one HSYNC pulse width
with 1/16 LSB resolution - the last 4-bits of the measurement
will be fractional.
0x43
HSYNC Width LSB,
(read only)
7:0
HSYNC Width LSB
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL51002
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