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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ISL26313FBZ-T7A |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 22/23闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 12BIT SPI/SRL 125K 8SOIC |
| 妯欐簴鍖呰锛� | 250 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 125k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 80mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 2 鍊嬪柈绔�锛屽柈妤� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�鐣�(d膩ng)鍓嶇22闋�绗�23闋�
ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319
8
FN7549.2
February 26, 2014
tACQ
Acquisition time in Auto Power-Down
Mode
150
s
tSCLKH
SCLK High Time
20
ns
tSCLKL
SCLK Low Time
20
ns
tCNV
CNV Pulse Width
100
ns
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The device may become nonresponsive if the minimum acquisition times are not met in their respective modes, requiring a power cycle to restore
normal operation.
8. Transition time to high impedance state is dominated by RC loading on the SDOUT pin. Specified value is measured using equivalent loading shown
in Figure 2.
Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40掳C to +125掳C (typical performance
at +25掳C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40掳C to +125掳C. (Continued)
SYMBOL
PARAMETER
TEST LEVEL OR NOTES
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
FIGURE 2. EQUIVALENT LOAD CIRCUIT FOR DIGITAL OUTPUT TESTING
OUTPUT PIN
CL
10pF
VDD
2k
RL
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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