19 FN7549.2 February 26, 2014 FIGURE 34. TIMING DIAGRAM FOR READING DURING" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ISL26313FBZ-T7A
寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 11/23闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC ADC 12BIT SPI/SRL 125K 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 250
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 125k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛孲PI?
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 1
鍔熺巼鑰楁暎锛堟渶澶э級锛� 80mW
闆诲闆绘簮锛� 鍠浕婧�
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 甯跺嵎 (TR)
杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� 2 鍊嬪柈绔紝鍠サ
ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319
19
FN7549.2
February 26, 2014
FIGURE 34. TIMING DIAGRAM FOR READING DURING CONVERSION MODE WITH EOC ON SDO OUTPUT
FIGURE 35. TIMING DIAGRAM FOR READING SPANNING CONVERSIONS MODE WITH EOC ON SDO OUTPUT
FIGURE 36. TIMING DIAGRAM FOR READING AFTER CONVERSION WITH REGISTER READBACK, WITHOUT EOC
Idle
CNV
SCLK
SDI
SDO
D15
D14
. . .
D14
. . .
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Acquisition
Conversion
tACQ
tSCLK
tCNV_CLK
tSCLKL
tDATA
tCNV
Conversion N
Conversion N+1
Configuration N+1
Conversion Result N-1
Configuration N+2
Conversion Result N
tSCLKH
MSB
MSB-1
D1
LSB
MSB
MSB-1
D1
tSDO_V
tSDI_H
tSDI_SU
Hi-Z State
D5
D4
D5
D4
Idle
CNV
SCLK
SDI
SDO
D15
D4
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Idle
Acquisition
Conversion
tACQ
tSCLK
tCNV_SCLK
tSCLKL
Conversion N
Conversion N+1
Configuration N+1
Conversion Result N-1
Configuration N+2
Conversion Result N
tSCLKH
MSB
MSB-1
D1
LSB
Hi-Z State
MSB
MSB-1
D1
tSDO_V
tSDI_H
tSDI_SU
D15
D14
D4
. . .
MSB-1 MSB-2
. . .
MSB-1
MSB-2
Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum tACQ is satisfied).
tDATA
tCNV
D14
. . .
D12
D13
D12
D13
. . .
CNV
SCLK
SDI
SDO
MSB
MSB-1
D15
D14
. . .
D1
LSB
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Idle
Configuration N+1
Conversion Result N-1
Hi-Z State
Conversion N
Cfg15
Cfg14
. . .
Cfg1
Cfg0
Configuration settings of N-1 Result
D5
D4
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-B6L-IV-F1 CONVERTER MOD DC/DC 28V 150W
VI-B6K-IV-F4 CONVERTER MOD DC/DC 40V 150W
ISL26323FBZ-T IC ADC 12BIT SPI/SRL 250K 8SOIC
IDT7207L15JG IC FIFO 16384X18 15NS 32PLCC
IDT7207L15J IC FIFO 16384X18 15NS 32PLCC
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ISL26314 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels
ISL26314FVZ 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:ISL26314FVZ 12-BIT, 125KSPS, 4-CHANNEL, DIFFERENTIAL SAR ADC - Rail/Tube
ISL26314FVZ-T 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:ISL26314FVZ 12-BIT, 125KSPS, 4-CHANNEL, DIFFERENTIAL SAR ADC - Tape and Reel
ISL26314FVZ-T7A 鍔熻兘鎻忚堪:IC ADC 12BIT SRL/SPI 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 浣嶆暩(sh霉):10 閲囨ǎ鐜囷紙姣忕锛�:357k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:830µW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:10-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:10-TDFN-EP锛�3x3锛� 鍖呰:鍓垏甯� (CT) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤碉紱2 鍊嬪柈绔�锛岄洐妤�锛�1 鍊嬪樊鍒嗭紝鍠サ锛�1 鍊嬪樊鍒嗭紝闆欐サ 鐢�(ch菐n)鍝佺洰閷勯爜闈�:1396 (CN2011-ZH PDF) 鍏跺畠鍚嶇ū:MAX1395ETB+TCT
ISL26315 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels