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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ISL26313FBZ-T7A |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/23闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 12BIT SPI/SRL 125K 8SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 250 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 125k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 80mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 2 鍊�(g猫)鍠锛屽柈妤� |
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ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319
18
FN7549.2
February 26, 2014
Reading After Conversion Mode, with EOC
In this mode (Figure 33), after CNV is asserted Low to start input
acquisition, a data exchange is executed by SCLK during the
Acquisition period. CNV is asserted High briefly to initiate a
Conversion, forcing SDO to a high-impedance state. SDO returns
HIGH when CNV is asserted Low during the entire conversion period.
At the end of conversion, the device asserts SDO Low to indicate
that the conversion is complete. This may be used as an interrupt
to start the Acquisition phase. It should be noted (as indicated in
Figure 33) that an additional pulse on CNV is required at the end
of conversion to take the part back to Acquisition from Idle state.
As discussed in section 鈥淩eading After Conversion Mode Without
throughput at slower SPI clock rates.
Reading During Conversion Mode, with EOC
From Idle, a falling edge on CNV initiates the Acquisition mode,
and then a rising edge initiates a Conversion. After the
conversion is initiated, CNV is asserted Low once again. Data
exchange across SDI and SDO can proceed while CNV is Low,
again observing the requirements of the tDATA period in order to
minimize the effects of digital noise on sensitive portions of the
conversion. In this mode, an additional pulse is required on SCLK
after the completion of the data exchange, to transition SDO to
the high-impedance state. Later, SDO is asserted low by the
device indicating end of conversion. The device then returns to
Idle. The falling edge of SDO may be used as an interrupt to start
the Acquisition phase (see Figure 34).
Reading Spanning Conversion Mode, with EOC
After initiating an Acquisition by bringing CNV Low, the user
begins exchanging data as previously mentioned, until CNV is
asserted High to initiate a conversion and SDO returns to a
high-impedance state, interrupting the exchange. And, after CNV
is returned Low, SDO will return to the state prior to the CNV
pulse in order to avoid losing data interrupted by the conversion
pulse (see Figure 35). The user should take care to observe the
tDATA period in order to minimize the effects of digital noise on
sensitive portions of conversion. After completion of the data
exchange, an additional pulse on SCLK forces SDO to a
high-impedance state. At the end of conversion, the device
asserts SDO Low indicating the end of conversion. The device
then returns to Idle, waiting for a pulse on CNV to initiate a new
Acquisition cycle.
Accessing the Configuration Register During
Data Readback
The Configuration Register contains the channel address of the
current conversion data. The contents can be accessed during a
normal data output sequence by continuing to clock data from
SDO if the register readback mode is enabled. Both 12-bit output
data words and the 16-bit configuration word are output in 28
SCLK periods, as shown in Figure 36, which demonstrates an
example sequence. Note that SDO goes into the high-impedance
state when CNV is High. The Configuration Register can be read
during any Read Sequence by generating the additional SCLKs,
with the restriction that the sequence must be completed prior to
the end of the current conversion. This will prevent loss of data
due to overwriting of the new conversion data into the output and
configuration registers.
FIGURE 33. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE WITH EOC ON SDO OUTPUT
Acq.
Acquisition
CNV
SCLK
SDI
SDO
MSB
MSB-1
D15
D14
. . .
D1
LSB
ADC STATE
Idle
Power-Up
Acquisition
Conversion
Idle
tACQ
tSCLK
tSDO_V
tSCLKL
Conversion N+1
Configuration N+1
Conversion Result N-1
tSCLKH
MSB
MSB-1
D15
D14
. . .
LSB
Configuration N+2
Conversion Result N
Conversion
Idle
tCNV_SCLK
tSDI_H
tSDI_SU
Hi-Z State
tCNV
Conversion N
D5
D4
D5
D4
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| VI-B6L-IV-F1 | CONVERTER MOD DC/DC 28V 150W |
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| ISL26323FBZ-T | IC ADC 12BIT SPI/SRL 250K 8SOIC |
| IDT7207L15JG | IC FIFO 16384X18 15NS 32PLCC |
| IDT7207L15J | IC FIFO 16384X18 15NS 32PLCC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| ISL26314FVZ | 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:ISL26314FVZ 12-BIT, 125KSPS, 4-CHANNEL, DIFFERENTIAL SAR ADC - Rail/Tube |
| ISL26314FVZ-T | 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:ISL26314FVZ 12-BIT, 125KSPS, 4-CHANNEL, DIFFERENTIAL SAR ADC - Tape and Reel |
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