
ISL24202
6
FN7587.0
March 15, 2011
Application Information
LCD panels have a VCOM (common voltage) that must be precisely
set to minimize flicker. Figure 3 shows a typical VCOM adjustment circuit using a mechanical potentiometer, and the equivalent
circuit replacement using the ISL24202. Having a digital counter
interface enables automatic, digital flicker minimization during
production test and alignment. After programming, the counter
interface is not needed again - the ISL24202 automatically powers
up with the correct VCOM voltage programmed previously.
The ISL24202 uses a digitally controllable potentiometer (DCP),
with 256 steps of resolution (Figure
4) to change the current
drawn at the OUT pin, which then changes the voltage created by
the R1 - R2 resistor divider (Figure 5). The OUT voltage can then be buffered by an external amplifier (A2) to generate a buffered output
voltage (VCOM) capable of driving the VCOM input of an LCD panel.
The amount of current sunk is controlled by the setting of the
DCP, which is recalled at power-up from the ISL24202’s internal
EEPROM. The EEPROM is typically programmed during panel
manufacture. As noted in the “Electrical Specifications” section
on page 4, the ISL24202 requires a minimum AVDD voltage of 10.8V for EEPROM programming, but will work in normal
operation down to 4.5V after the EEPROM has been
programmed, with no additional EEPROM writing.
DCP (Digitally Controllable Potentiometer)
The DCP controls the voltage that ultimately controls the SET
current. Figure
4 shows the relationship between the register
value and the DCP’s tap position. Note that a register value of 0
selects the first step of the resistor string. The output voltage of
the DCP is given in Equation
1:
Output Current Sink
Figure
5 shows the schematic of the OUT current sink. The
combination of amplifier A1, transistor Q1, and resistor RSET
forms a voltage-controlled current source, with the voltage
determined by the DCP setting.
The external RSET resistor sets the full-scale (maximum) sink current
that can be pulled from the OUT node. The relationship between
IOUT and Register Value is shown in Equation 2. The maximum value of IOUT can be calculated by substituting the
maximum register value of 255 into Equation
2, resulting in
Equation
2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation
4:FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
SET
ISL24202
R1
R2
AVDD
VCOM
IOUT
VDD
RSET
RA
RC
AVDD
VCOM
RB
R1 = RA
R2 = RB+RC
RSET = RARB + RARC
20RB
OUT
A2
VDCP
RegisterValue 1
+
256
---------------------------------------------------
AVDD
20
--------------
=
(EQ. 1)
FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP
AVDD
19R
R
0
1
2
255
254
253
252
251
REGISTER VALUE
AVDD
20
VDCP
FIGURE 5. CURRENT SINK CIRCUIT
AVDD
RSET
VDCP
SET
OUT
AVDD
IOUT
R1
R2
VSAT
Q1
A1
VOUT
VSET = VDCP = IOUT * RSET
IOUT
IOUT
VDCP
RSET
-------------
RegisterValue 1
+
256
---------------------------------------------------
AVDD
20
--------------
1
RSET
-------------
==
(EQ. 2)
IOUT MAX
()
AVDD
20RSET
--------------------
=
(EQ. 3)
ISTEP
AVDD
256
() 20
() R
SET
()
----------------------------------------------
=
(EQ. 4)