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參數(shù)資料
| 型號： | ISL24202IRTZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROG 8BIT VCOM CALIBRTR 8TDFN |
| 標準包裝： | 100 |
| 類型： | 校準器 |
| 應(yīng)用： | LCD 驅(qū)動器，基準電壓發(fā)生器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 管件 |
ISL24202
4
FN7587.0
March 15, 2011
Absolute Maximum Ratings
Thermal Information
Supply Voltage
AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET, CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD+0.3V
CE and WP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD+0.3V
Output Voltage with respect to Ground
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD
Continuous Output Current
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . .
53
11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For
θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5). Typicals are at
TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
DC CHARACTERISTICS
VDD
VDD Supply Range - Operating
2.25
3.6
V
AVDD
AVDD Supply Range Supporting EEPROM Programming
10.8
19
V
AVDD
AVDD Supply Range for Wide-Supply Operation without
EEPROM Programming
4.5
19
V
IDD
VDD Supply Current
CTL = 0.5*VDD
40
65
A
IAVDD
AVDD Supply Current
CTL = 0.5*VDD
24
38
A
OUT PIN CHARACTERISTICS
SETZSE
SET Zero-Scale Error
±3LSB
SETFSE
SET Full-Scale Error
±8LSB
VOUT
OUT Voltage Range
VSET + 1.75
AVDD
V
SETVD
SET Voltage Drift
7V/°C
IOUT
Maximum OUT Sink Current
4mA
INL
Integral Non-Linearity
±2LSB
DNL
Differential Non-Linearity
±1LSB
EEPROM CHARACTERISTICS
tPROG
EEPROM Programming Time (internal)
100
ms
UP/DOWN COUNTER CONTROL INPUTS (SEE FIGURE 11)
VIH
CE and CTL Input Logic High Threshold
0.7*VDD
V
VIL
CE and CTL Input Logic Low Threshold
0.3*VDD
V
ICS_PD
CE Input Pull Down Current Sink
0.5
1.5
A
ICTL
CTL Input Bias Current
CTL = GND (sourcing)
7
15
A
CTL = VDD (sinking)
7
15
A
tST
CE to CTL Start Delay
50
s
tREAD
EEPROM Recall Time (after CE de-asserted)
10
ms
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