2 FN7587.0 March 15, 2011 Block Diagram Pin Descriptions Pin Configuration ISL24202 (8 LD TDFN) TOP VIEW FIGURE 2. BLOCK DIAGRAM OF TH" />
參數(shù)資料
型號: ISL24202IRTZ
廠商: Intersil
文件頁數(shù): 5/12頁
文件大?。?/td> 0K
描述: IC PROG 8BIT VCOM CALIBRTR 8TDFN
標(biāo)準(zhǔn)包裝: 100
類型: 校準(zhǔn)器
應(yīng)用: LCD 驅(qū)動器,基準(zhǔn)電壓發(fā)生器
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN(3x3)
包裝: 管件
ISL24202
2
FN7587.0
March 15, 2011
Block Diagram
Pin Descriptions
Pin Configuration
ISL24202
(8 LD TDFN)
TOP VIEW
FIGURE 2. BLOCK DIAGRAM OF THE ISL24202
GND
DIGITAL
INTERFACE
DAC
REGISTERS
8-BIT EEPROM
CTL
DNC
CE
AVDD
SET
8
2
6
7
4
CS
OUT
1
Q1
A1
ANALOG DCP
AND
CURRENT SINK
UP/DOWN
COUNTER
5
VDD
3
VDD
RBIAS
PIN NAME PIN #
FUNCTION
OUT
1
Adjustable Sink Current Output Pin. The sink current into
the OUT pin is equal to the DAC setting times the
maximum adjustable sink current divided by 256. See
the “SET” pin function description below (pin 8) for
setting the maximum adjustable sink current.
AVDD
2
High-Voltage Analog Supply. Bypass to GND with 0.1F
capacitor.
DNC
3
Do Not Connect to external circuitry. It is acceptable to
ground this pin.
GND
4
Ground connection.
VDD
5
Digital power supply input. Bypass to GND with 0.1F
de-coupling capacitor.
CTL
6
Up/Down Control for internal counter and Internal
EEPROM Programming Control Input. When CE is high:
A low-to-mid transition increments the 8-bit counter,
adding 1 to the DAC setting, increasing the OUT sink
current, and lowering the divider voltage at the OUT pin.
A high-to-mid transition decrements the 8-bit counter,
subtracting 1 from the DAC setting, decreasing the OUT
sink current, and increasing the divider voltage at the
OUT pin.
To program the EEPROM, take this pin to >4.9V (see
“Electrical Specifications” table on page 5 for details).
Float when not in use.
CE
7
Counter Enable Pin. Connect CE to VDD to enable
adjustment of the output sink current. Float or connect
CE to GND to prevent further adjustment or
programming (Note: the CE pin has an internal 500nA
pull-down sink current). The EEPROM value will be
copied to the register on a VOH to VOL transition.
SET
8
Maximum Sink Current Adjustment Pin. Connect a
resistor from SET to GND to set the maximum
adjustable sink current of the OUT pin. The maximum
adjustable sink current is equal to (AVDD/20) divided
by RSET.
PAD
-
Thermal pad should be connected to system ground
plane to optimize thermal performance.
(*CONNECT THERMAL PAD TO GND)
OUT
AVDD
DNC
GND
1
2
3
4
8
7
6
5
SET
CE
CTL
VDD
PAD
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