參數(shù)資料
型號(hào): ISD5116P
廠商: WINBOND ELECTRONICS CORP
元件分類: 音頻合成
英文描述: Single-Chip Voice Record/Playback Device Up to 16-Minute Duration with Digital Storage Capability
中文描述: 960 SEC, SPEECH SYNTHESIZER WITH RCDG, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 50/57頁
文件大小: 735K
代理商: ISD5116P
October 2000
Page 49
9.2 I
2
C Protocol
Since the I2C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit that
indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is being
sent from the current bus master to the device being addressed. This single bit is a 0 for a Read cycle,
which indicates that the data is being sent from the device being addressed to the current bus master. For
example, the valid Slave Addresses for the ISD5116 device, for both Write and Read cycles, are shown in
Section 3.1.1
on page 9 of this datasheet.
Before any data is transmitted on the I2C interface, the current bus master must address the slave it
wishes to transfer data to or from. The Slave Address is always sent out as the 1
st
byte following the Start
Condition sequence. An example of a Master transmitting an address to a ISD5116 slave is shown below.
In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write cycle. All the bits
transferred are from the Master to the Slave, except for the indicated Acknowledge bits. The following
example details the transfer explained in
Section 3.1.2-3
on page 10 of this datasheet
.
Master Transmits to Slave Receiver (Write) Mode
S
W A
A
A
A
P
SLAVE ADDRESS
COMMAND BYTE
High ADDR. BYTE
Low ADDR. BYTE
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
Start Bit
Stop Bit
A common procedure in the ISD5116 is the reading of the Status Bytes. The Read Status condition in the
ISD5116 is triggered when the Master addresses the chip with its proper Slave Address, immediately
followed by the R/W bit set to a “0” and without the Command Byte being sent. This is an example of the
Master sending to the Slave, immediately followed by the Slave sending data back to the Master. The “N”
not-acknowledge cycle from the Master ends the transfer of data from the Slave. The following example
details the transfer explained in
Section 3.1.2-1
on page 9 of this datasheet.
Master Reads from Slave immediately after first byte (Read Mode)
R/W
From
M aster
Start Bit
From
M aster
Stop Bit
From
M aster
acknowledgement
from slave
acknowledgement
from M aster
not-acknowledged
from M aster
acknowledgement
from M aster
From M aster
From Slave
From Slave
From Slave
S
R
A
A
A
N
P
Low ADDR BYTE
SLAVE ADDRESS
STATUS WORD
High ADDR. BYTE
Another common operation in the ISD5116 is the reading of digital data from the chip’s memory array at a
specific address. This requires the I
2
C interface Master to first send an address to the ISD5116 Slave
device, and then receive data from the Slave in a single I
2
C operation. To accomplish this, the data
direction R/W bit must be changed in the middle of the command. The following example shows the
Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to the
ISD5116, and then immediately changing the data direction and reading some number of bytes from the
chip’s digital array. An unlimited number of bytes can be read in this operation. The “N” not-acknowledge
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ISD5116SI 功能描述:IC VOICE REC/PL 8-16MN IN 28SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標(biāo)準(zhǔn)包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續(xù)時(shí)間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:28-PDIP 其它名稱:90-21300+000