
101
1477K–AVR–08/10
ATtiny26(L)
ADC Multiplexer
Selection Register –
ADMUX
Bit 7, 6 – REFS1, REFS0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in
Table 45. If these bits are
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSR is set). The user should disregard the first conversion result after changing
these bits to obtain maximum accuracy. If differential channels are used, using AVCC or an
external AREF higher than (AVCC - 0.2V) is not recommended, as this will affect ADC accuracy.
The internal voltage reference may not be used if an external reference voltage is being applied
to the AREF pin.
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted.
Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongo-
Bits 4..0 – MUX4..MUX0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See
Table 46 for details. If these bits
are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSR is set).
Bit
765
4321
0
$07 ($27)
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
ADMUX
Read/Write
R/W
Initial Value
000
0000
0
Table 45. Voltage Reference Selections for ADC
REFS1
REFS0
Voltage Reference Selection
00
AVCC
0
1
AREF (PA3), Internal Vref turned off.
1
0
Internal Voltage Reference (2.56 V), AREF pin (PA3) not connected.
11
Internal Voltage Reference (2.56 V) with external capacitor at AREF pin
(PA3).