- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45378 > IR80C52TXXX-16SHXXX:RD (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 PDF資料下載
參數(shù)資料
| 型號(hào)： | IR80C52TXXX-16SHXXX:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 133/182頁(yè) |
| 文件大?。?/td> | 2994K |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)當(dāng)前第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)
54
1477K–AVR–08/10
ATtiny26(L)
DI/SDA/OC1A/PCINT0 – Port B, Bit 0
DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port
functions., so pin must be configure as an input.
SDA: Serial Data in USI Two-wire mode. Serial data pin is bi-directional and uses open-collector
output. The SDA pin is enabled by setting the pin as an output. The pin is pulled low when the
PORTB0 or USI shiftRegister is zero when DDB0 is set (one). Pull-up is disabled in USI Two-
wire mode.
OC1A: Inverted Timer/Counter1 PWM output A: The PB0 pin can serve as an Inverted output for
the PWM mode if not used in programming or USI. The PB0 pin has to be configured as an out-
put (DDB0 set (one)) to serve this function.
PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt
is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt.
The masking alternate functions are the inverted output compare match output OC1A and USI
data DI or SDA. Digital input is enabled on pin PB0 also in SLEEP modes, if the pin change
alternate functions of Port B to the overriding signals shown in “Alternate Port Functions” on
Notes: 1. RSTDISBL Fuse (active low) is described in section “System Control and Reset” on page 32.
2. Note that the PCINT1 Interrupt is only enabled if both the Global Interrupt Flag is enabled, the PCIE1 flag in GIMSK is set
and the alternate function of the pin is disabled as described in “Pin Change Interrupt” on page 62.
3. PB5IOENABLE and PB4IOENABLE are given by the PLLCK and CKSEL Fuses as described in “Clock Sources” on page
4. External low level interrupt is enabled if both the Global Interrupt Flag is enabled and the INT0 flag in GIMSK is set as
described in “External Interrupt” on page 62.
5. Not operator is marked with “~”.
6. The operation of the Timer/Counter0 with external clock disabled is described in “8-bit Timer/Counter0” on page 65.
7. External clock is selected by the PLLCK and CKSEL Fuses as described in “Clock Sources” on page 25.
Table 27. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PB7/ADC10/RESET/
PCINT1
PB6/ADC9/INT0/TO/
PCINT1
PB5/ADC8/XTAL2/
PCINT1
PB4/ADC7/XTAL1
PUOE
RSTDSBL(1)
~PB4IOENABLE(3)
PUOV
1
0
DDOE
RSTDSBL(1)
0
~PB5IOENABLE(3)
~PB4IOENABLE(3)
DDOV
0
PVOE
0
PVOV
0
DIEOE
~T0_EXT_CLOCK (6)
PCINT1_ENABLE(2) |
PCINT1_ENABLE(2) |
~PB5IOENABLE(3)
PCINT_ ENABLE (2) |
~PB4IOENABLE(3) |
EXT_CLOCK_ENABLE(7)
DIEOV
PCINT1_ENABLE(2)
1
PCINT1_ENABLE(2)
PB5IOENABLE(3)
PCINT1_ENABLE(2)
EXT_CLOCK_ENABLE
DI
PCINT1
INT0, T0, PCINT1
PCINT1
External Clock, PCINT1
AIO
ADC10, RESET INPUT
ADC9
ADC8, XTAL2
XTAL1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR80C32-25/883R | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| MR80C52CXXX-12SBR | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MR80C32-16SC | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MD80C32-30SCD | 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40 |
| MR83C154TXXX-20P883R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IR80C86-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| IR80C88 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| IR80C88-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| IR-820 | 制造商:BOWEI 制造商全稱:BOWEI 功能描述:Image Rejection Mixers |
| IR8200 | 制造商:IRF 制造商全稱:International Rectifier 功能描述:3A, 55V DMOS H-BRIDGE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。