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參數(shù)資料
| 型號： | IR80C52TXXX-16SHXXX:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 140/182頁 |
| 文件大小： | 2994K |
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60
1477K–AVR–08/10
ATtiny26(L)
Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match A, interrupt is enabled. The corresponding interrupt at vector
$003 is executed if a compare match A occurs. The Compare Flag in Timer/Counter1 is set
(one) in the Timer/Counter Interrupt Flag Register.
Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match B, interrupt is enabled. The corresponding interrupt at vector
$004 is executed if a compare match B occurs. The Compare Flag in Timer/Counter1 is set
(one) in the Timer/Counter Interrupt Flag Register.
Bit 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $005) is
executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the
Timer/Counter Interrupt Flag Register – TIFR.
Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is
executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0) is set (one) in the
Timer/Counter Interrupt Flag Register – TIFR.
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Timer/Counter
Interrupt Flag Register
– TIFR
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A
are set (one), the Timer/Counter1 A Compare Match interrupt is executed.
Bit 5 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1B – Output Compare Register 1A. OCF1B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B
are set (one), the Timer/Counter1 B Compare Match interrupt is executed.
Bits 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Bit
7
6
5
4
3
2
1
0
$38 ($58)
–
OCF1A
OCF1B
–
TOV1
TOV0
–
TIFR
Read/Write
R
R/W
R
R/W
R
Initial Value
0
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