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| 型號(hào)： | IR80C52TXXX-16SHXXX:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁(yè)數(shù)： | 161/182頁(yè) |
| 文件大?。?/td> | 2994K |
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8
1477K–AVR–08/10
ATtiny26(L)
concept enables instructions to be executed in every clock cycle. The program memory is In-
System programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly
accessed. All AVR instructions have a single 16-bit word format, meaning that every program
memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit
Stack Pointer SP is read/write accessible in the I/O space. For programs written in C, the stack
size must be declared in the linker file. Refer to the C user guide for more information.
The 128 bytes data SRAM can be easily accessed through the five different addressing modes
supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, Timer/Counters, and other I/O functions. The memory spaces in the AVR architecture are
all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt
Vector in the Interrupt Vector table at the beginning of the program memory. The different inter-
rupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt
Vector address, the higher the priority.
General Purpose
Register File
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
$00
R1
$01
R2
$02
…
R13
$0D
General
R14
$0E
Purpose
R15
$0F
Working
R16
$10
Registers
R17
$11
…
R26
$1A
X-register Low Byte
R27
$1B
X-register High Byte
R28
$1C
Y-register Low Byte
R29
$1D
Y-register High Byte
R30
$1E
Z-register Low Byte
R31
$1F
Z-register High Byte
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