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| 型號(hào)： | ICS1892 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁(yè)數(shù)： | 117/148頁(yè) |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892 |
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Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1892, Rev. D, 2/26/01
February 26, 2001
117
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
9.2.4.4
MAC/Repeater Interface Pins for Link Pulse Interface
Table 9-9
lists the MAC/Repeater Interface pin descriptions for the Link Pulse Interface.
Table 9-9.
MAC/Repeater Interface Pins: Link Pulse Interface
MII Pin
Name
Link
Pluse
Pin
Name
Pin
No.
Pin
Type
Pin Description
COL
–
49
No
Connect
Collision (Detect).
For the Link Pulse Interface, this pin is a no connect. For more
information, see
Table 6-3
.
CRS
–
50
No
Connect
Carrier Sense.
For the Link Pulse Interface, this pin is a no connect. For more
information, see
Table 6-3
.
RXER
LPRX
38
Output
Link Pulse (Interface) Receive Error.
This pin’s description is the same as that given in
Table 9-6
.
RXCLK
LRCLK
37
Output
Link (Pulse Interface) Receive Clock.
The ICS1892 sources the LRCLK to the MAC/repeater. The
ICS1892 uses LRCLK to synchronize the signals on the LPRX
pin. The signal on the LRCLK pin is conditioned by RXTRI.
MDC
MDC
31
Input
Management Data Clock.
This pin’s description is the same as that given in
Table 9-6
.
MDIO
MDIO
30
Input/
Output
Management Data Input/Output.
This pin’s description is the same as that given in
Table 9-6
.
RXD0,
RXD1,
RXD2,
RXD3
–
35,
34,
33,
32
No
Connect
Receive Data 0–3.
For the Link Pulse Interface, these pins are a no connect. For
more information, see
Table 6-3
.
RXDV
–
36
No
Connect
Receive Data Valid.
For the Link Pulse Interface, this pin is a no connect. For more
information, see
Table 6-3
.
RXER
LPRX
38
Output
Link Pulse (Interface) Receive Error.
This pin’s description is the same as that given in
Table 9-6
.
RXTRI
39
Input
Receive (Interface), Tri-State.
The input on this pin is from a MAC. When the signal on this pin is
logic:
Low, the MAC indicates that it is not in a tri-state condition.
High, the MAC indicates that it is in a tri-state condition. In this
case, the ICS1892 acts to ensure that only one PHY is active
at a time.
TXCLK
LTCLK
43
Link (Pulse Interface) Transmit Clock.
This pin’s description is the same as that given in
Table 9-6
.
TXD0,
TXD1,
TXD2,
TXD3
–
45,
46,
47,
48
No
Connect
Transmit Data 0–3.
For the Link Pulse Interface, these pins are a no connect. For
more information, see
Table 6-3
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-10 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
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