
ICS1892, Rev. D, 2/26/01
February 26, 2001
114
Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
RXD0,
RXD1,
RXD2,
RXD3
SRD0,
SRD1,
SRD2,
SRD3
35,
34,
33,
32
Symbol Receive Data 0–3.
SRD0 is the least-significant bit and SRD3 is the
most-significant bit of the MII receive data nibble.
While the ICS1892 asserts RXDV, the ICS1892 transfers the
receive data signals on the SRD0–SRD3 pins to the
MAC/Repeater Interface synchronously on the rising edges
of SRCLK.
RXDV
–
36
No
Connect
Receive Data Valid.
For the 100M Symbol Interface, this pin is a no connect. For
more information, see
Table 6-1
.
RXER
SRD4
38
Output
Symbol Receive Data 4.
This pin’s description is the same as that given in
Table 9-6
.
RXTRI
39
Input
Receive (Interface), Tri-State.
The input on this pin is from a MAC. When the signal on this pin
is logic:
Low, the MAC indicates that it is not in a tri-state condition.
High, the MAC indicates that it is in a tri-state condition. In
this case, the ICS1892 acts to ensure that only one PHY is
active at a time.
TXCLK
STCLK
43
Symbol Transmit Clock.
This pin’s description is the same as that given in
Table 9-6
. For
100Base-Tx
TXD0–3
STD0,
STD1,
STD2,
STD3
45,
46,
47,
48
Input
Symbol Transmit Data 0–3.
STD0 is the least-significant bit and STD3 is the
most-significant bit of the MII transmit data nibble received
from the MAC/repeater.
While the ICS1892 asserts TXEN, the signals on the
STD0–3 pins are sampled by the ICS1892 synchronously on
the rising edges of STCLK.
TXEN
–
44
No
Connect
Transmit Enable.
For the 100M Symbol Interface, this pin is a no connect. For
more information, see
Table 6-1
.
TXER
STD4
42
Input
Symbol Transmit Data 4.
This pin’s description is the same as that given in
Table 9-6
.
Table 9-7.
MAC/Repeater Interface Pins: 100M Symbol Interface (
Continued
)
MII Pin
Name
100M
Symbol
Pin
Name
Pin
No.
Pin
Type
Pin Description