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參數(shù)資料
| 型號(hào)： | HYB39S256160T |
| 廠商： | SIEMENS AG |
| 英文描述： | 256 MBit Synchronous DRAM(256M位同步動(dòng)態(tài)RAM) |
| 中文描述： | 256兆比特同步DRAM（256M位同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 594K |
| 代理商： | HYB39S256160T |
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HYB39S256400/800/160AT
256 MBit Synchronous DRAM
20
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. AC- Parameters
8.1 AC Parameters for a Write Timing
8.2 AC Parameters for a Read Timing
9. Mode Register Set
10. Power on Sequence and Auto Refresh (CBR)
11. Clock Suspension (using CKE)
11. 1 Clock Suspension During Burst Read CAS Latency = 2
11. 2 Clock Suspension During Burst Read CAS Latency = 3
11. 3 Clock Suspension During Burst Write CAS Latency = 2
11. 4 Clock Suspension During Burst Write CAS Latency = 3
12. Power Down Mode and Clock Suspend
13. Self Refresh ( Entry and Exit )
14. Auto Refresh ( CBR )
15. Random Column Read ( Page within same Bank)
15.1 CAS Latency = 2
15.2 CAS Latency = 3
16. Random Column Write ( Page within same Bank)
16.1 CAS Latency = 2
16.2 CAS Latency = 3
17. Random Row Read ( Interleaving Banks) with Precharge
17.1 CAS Latency = 2
17.2 CAS Latency = 3
18. Random Row Write ( Interleaving Banks) with Precharge
18.1 CAS Latency = 2
18.2 CAS Latency = 3
19. Precharge Termination of a Burst
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相關(guān)代理商/技術(shù)參數(shù) |
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| HYB39S256160T-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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| HYB39S256160TC-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
| HYB39S256160TC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
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