參數(shù)資料
型號: HYB25D512800BE-6
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512Mbit Double Data Rate SDRAM
中文描述: 512MB的雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 56/90頁
文件大?。?/td> 3191K
代理商: HYB25D512800BE-6
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
56
Rev. 1.2, 2004-06
Note:
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Table 10
Current State CKE n-1
Truth Table 2: Clock Enable (CKE)
CKEn
Previous
Cycle
Cycle
L
L
L
H
L
L
L
H
All Banks Idle
H
All Banks Idle
H
Bank(s) Active H
H
Command n
Action n
Notes
Current
Self Refresh
Self Refresh
Power Down
Power Down
X
Deselect or NOP
X
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See
Table 11
Maintain Self-Refresh
Exit Self-Refresh
Maintain Power-Down
Exit Power-Down
Precharge Power-Down Entry –
Self Refresh Entry
Active Power-Down Entry
1)
2)
L
L
L
H
1)
V
REF
must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (
t
XSNR
) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Table 11
Current State CS
Any
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
RAS CAS WE
Command
H
X
X
X
Deselect
L
H
H
H
No Operation
L
L
H
H
Active
L
L
L
H
AUTO REFRESH
L
L
L
L
MODE
REGISTER SET
L
H
L
H
Read
L
H
L
L
Write
L
L
H
L
Precharge
L
H
L
H
Read
Action
NOP. Continue previous operation.
NOP. Continue previous operation.
Select and activate row
Notes
1)2)3)4)5)6)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see
Table 10
and after
t
XSNR
/
t
XSRD
has been met (if the
previous state was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
1) to 6)
Idle
1) to 6)
1) to 7)
1) to 7)
Row Active
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
Select column and start new Read
burst
Truncate Read burst, start
Precharge
BURST TERMINATE
1) to 6), 8)
1) to 6),
8)
1) to 6), 9)
Read (Auto
Precharge
Disabled)
1) to 6),
8)
L
L
H
L
Precharge
1) to 6),
9)
L
H
H
L
BURST
TERMINATE
Read
Write
Precharge
1) to 6),
10)
Write (Auto
Precharge
Disabled)
L
L
L
H
H
L
L
L
H
H
L
L
Select column and start Read burst
Select column and start Write burst
Truncate Write burst, start Precharge
1) to 6),
8),
11)
1) to 6),
8)
1) to 6),
9),
11)
相關(guān)PDF資料
PDF描述
HYB25D512160BE-6 512Mbit Double Data Rate SDRAM
HYB25D512400BE-7 512Mbit Double Data Rate SDRAM
HYB25D512160TE-3 122 x 32 pixel format, LED Backlight available
HYB25L128160AC-75 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES
HYB25L128160AC 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D512800CE-5 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB25D512800CE-6 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP(0.300",7.62mm) 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB25DC512160CE-5 制造商:Infineon Technologies AG 功能描述: 制造商:QIMONDA 功能描述:
HYB25L256160AC-7.5 制造商:Infineon Technologies AG 功能描述:
HYB25L512160AC-7.5 制造商:Rochester Electronics LLC 功能描述:- Bulk