參數(shù)資料
型號(hào)： HYB25D512400BE-6
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512Mbit Double Data Rate SDRAM
中文描述： 512MB的雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 72/90頁(yè)
文件大?。?/td> 3191K
代理商： HYB25D512400BE-6
Data Sheet
72
Rev. 1.2, 2004-06
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Normal Strength Pull-down and Pull-up Characteristics
5.2.1
I
DD
Current Measurement Conditions
I
DD1
: Operating Current: One Bank Operation
1. Only one bank is accessed with
t
RCMIN
. Burst Mode, Address and Control inputs on NOP edge are changing
once per clock cycle.
I
OUT
= 0 mA.
2. Timing patterns
a)
DDR266A
(133 MHz, CL = 2):
t
CK
= 7.5 ns, CL = 2, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 9
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing
50% of data changing at every burst
b)
DDR333
(166 MHz, CL = 2.5):
t
CK
= 6 ns, CL = 2.5, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 9
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing
50% of data changing at every burst
c)
DDR400
(200 MHz, CL = 3):
t
CK
= 5 ns, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 11
×
t
CK
,
t
RAS
= 8
×
t
CK
Setup: A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
50% of data changing at every burst
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
I
DD7
: Operating Current: Four Bank Operation
1. Four banks are being interleaved with
t
RCMIN
. Burst Mode, Address and Control inputs on NOP edge are not
changing.
I
OUT
= 0 mA.
2. Timing patterns
a)
DDR266A
(133 MHz, CL = 2):
t
CK
= 7.5 ns, CL = 2, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3
×
t
CK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
b)
DDR333
(166 MHz, CL = 2.5):
t
CK
= 6 ns, CL = 2.5, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3
×
t
CK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
c)
DDR400
(200 MHz, CL = 3):
t
CK
= 5 ns, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 11
×
t
CK
,
t
RAS
= 8
×
t
CK
Setup: A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
50% of data changing at every burst
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
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