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參數(shù)資料
| 型號： | HYB25D512400AT-7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512Mbit Double Data Rate SDRAM |
| 中文描述： | 512MB的雙倍數(shù)據速率SDRAM |
| 文件頁數(shù)： | 85/90頁 |
| 文件大?。?/td> | 3191K |
| 代理商： | HYB25D512400AT-7 |
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HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
System Characteristics for DDR SDRAMs
Data Sheet
85
Rev. 1.2, 2004-06
08122003-RMYD-6BJP
7
System Characteristics for DDR SDRAMs
The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to
ensure proper system performance. These characteristics are for system simulation purposes and are guaranteed
by design.
Table 21
Input Slew Rate for DQ, DQS, and DM
AC Characteristics
Symbol
Parameter
DM/DQS inout slew rate measured berween
V
IH(DC)
,
V
IL (DC)
, and
V
IL(DC)
,
V
IH (DC)
DDR400
Min. Max. Min. Max. Min. Max.
0.5
4.0
0.5
DDR333
DDR266
Units Notes
DCSLEW
4.0
0.5
4.0
V/ns
1)2)
1) Pullup slew rate is characterized under the test conditions as shown in
Figure 52
.
2) DQS, DM, amd DQ input slew rate is specified to prevent doble clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
Table 22
Input Slew Rate
0.5 V/ns
0.4 V/ns
0.3 V/ns
Input Setup & Hold Time Derating for Slew Rate
t
IS
0
+50
+100
t
IH
0
0
0
Units
ps
ps
ps
Notes
1)
1)
A derating factor will be used to increase
t
and
t
in the case where the input slew rate is below 0.5 V/ns as
shown in
Table 22
. The input slew rate is based on the lesser of the slew rates determined by either
V
to
V
or
V
to
V
, similarly for rising transitions. Aderating factor applies to speed bins DDR200,
DDR266, and DDR333.
Table 23
I/O Input Slew Rate
0.5 ns/V
0.4 ns/V
0.3 ns/V
Input/Output Setup and Hold TIme Derating for Slew Rate
t
DS
0
+75
+100
t
DH
0
+75
+100
Units
ps
ps
ps
Notes
1)
1)
Table 23
is used to increase
t
and
t
in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew
rate is based on the lesser of the AV – AC slew rate and the DC – DC slew rate. The input slew rate is based
on the lesser of the slew rates determined by either
V
to
V
or
V
to
V
, and similarly for rising
transitions. A derating factor applies to speed bins DDR200, DDR266 and DDR333.
Table 24
Delta Slew Rate
±
0.0 ns/V
±
0.25 ns/V
±
0.5 ns/V
Input/Output Setup and Hold Derating for Rise/Fall Delta Slew Rate
t
DS
0
+
50
+
100
t
DH
0
+
50
+
100
Units
ps
ps
ps
Notes
1)
1) A derating factor will be used to increase
t
DS
and
t
DH
in the case where DQ, DM and DQS slew rates differ, as shown in
Tables 15 & 16. Input slew rate is based on the larger of AC – AC delta rise, fall rate and DC – DC delta rise, fall rate. Input
slew rate is based on the lesser of the slew rates determined by either
V
IH (AC)
to
V
IL (AC)
or
V
IH (DC)
to
V
IL (DC)
, similarly for
rising transitions.
The delta rise/fall rate is calculated as:{1/(Slew Rate1)} – {1/(Slew Rate2)}
For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is –0.5 ns/V. Using the
table given, this would result in the need for an increase in
t
DS
and
t
DH
of 100 ps. A derating factor applies to speed bins
DDR200, DDR266, and DDR333.
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| HYB25D512800CE-5 | 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產品目錄頁面:1449 (CN2011-ZH PDF) |
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