參數(shù)資料
型號(hào)： HYB25D512400AT-7
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512Mbit Double Data Rate SDRAM
中文描述： 512MB的雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 70/90頁(yè)
文件大小： 3191K
代理商： HYB25D512400AT-7
Data Sheet
70
Rev. 1.2, 2004-06
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Normal Strength Pull-down and Pull-up Characteristics
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between
V
IH(ac)
and
V
IL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 19
Parameter
Operating Current:
one bank; active/ precharge;
t
RC
=
t
RCMIN
;
t
CK
=
t
CKMIN
;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once
every two clock cycles.
Operating Current:
one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current:
all banks idle; power-down mode; CKE
≤
V
ILMAX
;
t
CK
=
t
CKMIN
Precharge Floating Standby Current:
CS
≥
V
IHMIN
, all banks idle;
CKE
≥
V
IHMIN
;
t
CK
=
t
CKMIN
, address and other control inputs changing once per clock cycle,
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current:
CS
≥
V
IHMIN
, all banks idle; CKE
≥
V
IHMIN
;
t
CK
=
t
CKMIN
, address and other control inputs stable
at
≥
V
IHMIN
or
≤
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Power-Down Standby Current:
one bank active; power-down mode;
CKE
≤
V
ILMAX
;
t
CK
=
t
CKMIN
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Standby Current:
one bank active; CS
≥
V
IHMIN
; CKE
≥
V
IHMIN
;
t
RC
=
t
RASMAX
;
t
CK
=
t
CKMIN
;
DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per
clock cycle.
Operating Current:
one bank active; Burst = 2; reads; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
t
CK
=
t
CKMIN
;
I
OUT
= 0 mA
Operating Current:
one bank active; Burst = 2; writes; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
t
CK
=
t
CKMIN
Auto-Refresh Current:
t
RC
=
t
RFCMIN
, burst refresh
Self-Refresh Current:
CKE
≤
0.2 V; external clock on;
t
CK
=
t
CKMIN
Operating Current:
four bank; four bank interleaving with BL = 4; Refer to the following page for
detailed test conditions.
I
DD
Conditions
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
相關(guān)PDF資料
PDF描述
HYB25D512800BE-5 512Mbit Double Data Rate SDRAM
HYB25D512160BE-5 512Mbit Double Data Rate SDRAM
HYB25D512400BE-6 512Mbit Double Data Rate SDRAM
HYB25D512800BE-6 512Mbit Double Data Rate SDRAM
HYB25D512160BE-6 512Mbit Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D512400BR-7 制造商:Infineon Technologies AG 功能描述:128M X 4 DDR DRAM MODULE, P66 Pin Plastic SMT
HYB25D512400CE-5 制造商:Infineon Technologies AG 功能描述:
HYB25D512800CE-5 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF)
HYB25D512800CE-6 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁(yè)面:1449 (CN2011-ZH PDF)
HYB25DC512160CE-5 制造商:Infineon Technologies AG 功能描述: 制造商:QIMONDA 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*