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參數(shù)資料
| 型號(hào)： | HYB25D512400AT-7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512Mbit Double Data Rate SDRAM |
| 中文描述： | 512MB的雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 31/90頁 |
| 文件大小： | 3191K |
| 代理商： | HYB25D512400AT-7 |
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Data Sheet
31
Rev. 1.2, 2004-06
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
3.5.2
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are
initiated with a Read command, as shown on
Figure 9
.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge
at the completion of the burst, provided
t
RAS
has been satisfied. For the generic Read commands used in the
following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the CAS
latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or
negative clock edge (i.e. at the next crossing of CK and CK).
Figure 10
shows general timing for each supported
CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is
known as the read preamble; the low state coincident with the last data-out element is known as the read post
amble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z. Data
from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In
either case, a continuous flow of data can be maintained. The first data element from the new burst follows either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new Read command should be issued x cycles after the first Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n pre fetch architecture). This is shown on
Figure 11
. A
Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read
data is illustrated on
Figure 12
. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
within a page (or pages) can be performed as shown on
Figure 13
.
Data from any Read burst may be truncated with a Burst Terminate command, as shown on
Figure 14
. The Burst
Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles
after the Read command, where x equals the number of desired data element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must be used, as shown on
Figure 15
. The example is
shown for
t
DQSS(min)
. The
t
DQSS(max)
case, not shown here, has a longer bus idle time.
t
DQSS(min)
and
t
DQSS(max)
are
defined in
Chapter 3.5.3
.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto
Precharge was not activated). The Precharge command should be issued x cycles after the Read command,
where x equals the number of desired data element pairs (pairs are required by the 2n prefect architecture). This
is shown on
Figure 16
for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent
command to the same bank cannot be issued until
t
RP
is met. Note that part of the row precharge time is hidden
during the access of the last data elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as
described above) provides the same operation that would result from the same Read burst with Auto Precharge
enabled. The disadvantage of the Precharge command is that it requires that the command and address busses
be available at the appropriate time to issue the command. The advantage of the Precharge command is that it
can be used to truncate bursts.
Reads
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D512400BR-7 | 制造商:Infineon Technologies AG 功能描述:128M X 4 DDR DRAM MODULE, P66 Pin Plastic SMT |
| HYB25D512400CE-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB25D512800CE-5 | 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB25D512800CE-6 | 功能描述:IC DDR SDRAM 512MBIT 66TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB25DC512160CE-5 | 制造商:Infineon Technologies AG 功能描述: 制造商:QIMONDA 功能描述: |
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