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參數資料
| 型號： | HYB25D256400T-8 |
| 英文描述： | DDR Synchronous DRAM |
| 中文描述： | DDR同步DRAM |
| 文件頁數： | 58/76頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | HYB25D256400T-8 |
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HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Page 58 of 76
2002-05-06
AC Characteristics
(
N
otes 1-5 apply to the following Tables;
E
lectrical Characteristics and DC Operating Conditions, AC Operating
Conditions, I
DD
Specifications and Conditions, and
E
lectrical Characteristics and AC Timing.)
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The figure below represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing ref-
erence load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
4. AC timing and I
DD
tests may use a V
IL
to V
I
H
swing of up to 1.5V in the test environment, but input timing is still refer-
enced to V
R
E
F
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC
input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between
V
IL(AC)
and V
I
H
(AC)
.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not
ring back above (below) the DC input LO
W
(
H
I
GH
) level)
6. For System Characteristics like Setup
& H
oldtime Derating for Slew Rate, I/O Delta Rise/Fall Derating,DDR SDRAM
Slew Rate Standards, Overshoot
&
Undershoot specification and Clamp V-I characteristics see the latest
JE
D
E
C
specification for DDR components
AC Output Load Circuit Diagram / Timing Reference Load
AC Operating Conditions
(0 °C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V)
Symbol
Parameter/Condition
Min
Max
Unit
N
otes
V
I
H
(AC)
Input
H
igh (Logic 1) Voltage, DQ, DQS, and DM Signals
V
R
E
F
+
0.31
V
1, 2
V
IL(AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
V
R
E
F
0.31
V
1, 2
V
ID(AC)
Input Differential Voltage, CK and CK Inputs
0.7
V
DDQ
+
0.6
V
1, 2, 3
V
I
X
(AC)
Input Closing Point Voltage, CK and CK Inputs
0.5
*
V
DDQ
0.2 0.5
*
V
DDQ
+
0.2
V
1, 2, 4
1. Input slew rate = 1V/ns
.
2. Inputs are not recognized as valid until V
R
E
F
stabilizes.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V
I
X
is expected to equal 0.5
*
V
DDQ
of the transmitting device and must track variations in the DC level of the same.
50
Timing Reference Point
Output
(V
OUT
)
30pF
V
TT
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|---|---|
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB25D256800AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mbit (32Mx8) DDR266A (2-3-3)? |
| HYB25D256800AT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYB25D256800AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYB25D256800BC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256-Mbit Double Data Rate SDRAM, Die Rev. B |
| HYB25D256800BC-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256Mb (64Mx4) FBGA DDR266A (2-3-3)? |
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